FUJITSU SEMICONDUCTOR DS07-13713-3E DATA SHEET 16-bit Proprietary Microcontroller CMOS 2 F MC-16LX MB90495G Series MB90497G/F497G/F498G/V495G n DESCRIPTION The MB90495G Series is a general-purpose, high-performance 16-bit microcontroller. It was designed for devices like consumer electronics, which require high-speed, real-time process control. This series features an on-chip full-CAN interface. 2 In addition to being backwards compatible with the F MC* family architecture, the instruction set has been ex- panded to add support for high-level language instructions, expanded addressing mode, and enhanced multiply/ divide and bit processing instructions. A 32-bit accumulator is also provided, making it possible to process long word (32-bit) data. The MB90495G Series peripheral resources include on chip 8/10-bit A/D converter, UART (SCI) 0/1, 8/16-bit PPG timer, 16-bit I/O timer (16-bit free-run timer, input capture 0, 1, 2, 3 (ICU) ) , and CAN controller. 2 2 * : F MC is abbreviation for Fujitsu Flexible Microcontroller. F MC is a registered trademark of Fujitsu Limited. n FEATURES Models that support +125 C Clock Built-in PLL clock multiplier circuit Choose 1/2 oscillation clock or 1 to 4 multiplied oscillation clock (for a 4-MHz oscillation clock, 4 to 16 MHz) machine (PLL) clock (Continued) n PACKAGES 64-pin plastic QFP 64-pin plastic LQFP (FPT-64P-M06) (FPT-64P-M09) MB90495G Series (Continued) Select subclock behavior (8.192 kHz) Minimum instruction execution time : 62.5 ns (operating with 4-MHz oscillation clock and 4 PLL clock) 16-MByte CPU memory space 24-bit internal addressing External access possible through selection of 8/16-bit bus width (external bus mode) Optimum instruction set for controller applications Wealth of data types (Bit, Byte, Word, Long Word) Wealth of addressing modes (23 different modes) Enhanced signed multiply-divide instructions and RETI instruction functions Enhanced high-precision arithmetic employing 32-bit accumulator Instruction set supports high-level programming language (C) and multitasking Employs system stack pointer Enhanced indirect instructions with all pointer types Barrel shift instructions Improved execution speed 4-byte instruction queue Powerful interrupt feature Powerful 8-level, 34-condition interrupt feature CPU-independent automated data forwarding 2 Extended intelligent I/O service feature (EI OS) : maximum 16 channels Low-power consumption (Standby) Mode Sleep mode (CPU operation clock stopped) Time-base timer mode (oscillation clock and subclock, time-base timer and watch timer only operational) Watch mode (subclock and watch timer only operational) Stop mode (oscillation clock and subclock stopped) CPU intermittent operation mode Process CMOS technology I/O Ports Generic I/O ports (CMOS output) : 49 Timer Time-base timer, watch timer, watchdog timer : 1 channel 8/16-bit PPG timer : four 8-bit channels, or two 16-bit channels 16-bit reload timer : 2 channels 16-bit I/O timer 16-bit free-run timer : 1 channel 16-bit input capture (ICU) : 4 channels Generates interrupt requests by latching onto the count value of the 16-bit free-run timer with pin input edge detection (Continued) 2