MB90F543G(S)/546G(S)/548G(S)/549G(S)/549G(S)/ V540GM/B90543G(S)/547G(S)/548G(S)/F548GL(S) 2 CMOS F MC-16LX MB90540G/545G Series 16-bit Proprietary Microcontroller The MB90540G/545G series with FULL-CAN and Flash ROM is specially designed for automotive and industrial applications. Its main features are on-board CAN Interfaces (MB90540G series: 2 channels, MB90545G series: 1 channel) , which conform to CAN V2.0A and V2.0B specifications, supporting very flexible message buffer scheme and so offering more functions than a normal full 2 2 CAN approach. The instruction set by F MC-16LX CPU core inherits an AT architecture of the F MC family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipula- tion instructions.The micro controller has a 32-bit accumulator for processing long word data.The MB90540G/545G series has peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial interfaces, 8/16-bit timer, I/O timer (input capture (ICU) , output compare (OCU) ) . Erase can be performed on each block Features Block protection with external programming voltage Clock Low-power consumption (stand-by) mode Embedded PLL clock multiplication circuit Sleep mode (mode in which CPU operating clock is Operating clock (PLL clock) can be selected from : divided- stopped) by-2 of oscillation or one to four times the oscillation Stop mode (mode in which oscillation is stopped) Minimum instruction execution time : 62.5 ns (operation at CPU intermittent operation mode oscillation of 4 MHz, PLL four times multiplied : Watch mode machine clock 16 MHz and at operating VCC = 5.0 V) Hardware stand-by mode Subsystem Clock : 32 kHz Process Instruction set to optimize controller applications 0.5 m CMOS technology Rich data types (bit, byte, word, long word) I/O port Rich addressing mode (23 types) General-purpose I/O ports : 81 ports Enhanced signed multiplication/division instruction and RETI instruction functions Timer Enhanced precision calculation realized by the 32-bit Watchdog timer : 1 channel accumulator 8/16-bit PPG timer : 8/16-bit 4 channels 16-bit reload timer : 2 channels Instruction set designed for high level language (C language) and multi-task operations 16-bit I/O timer Adoption of system stack pointer 16-bit free-run timer : 1 channel Enhanced pointer indirect instructions Input capture : 8 channels Barrel shift instructions Output compare : 4 channels Program patch function (for two address pointers) Extended I/O serial interface : 1 channel Enhanced execution speed : 4-byte Instruction queue UART0 With full-duplex double buffer (8-bit length) Enhanced interrupt function : 8 levels, 34 factors Clock asynchronized or clock synchronized (with start/stop Automatic data transmission function independent of CPU bit) transmission can be selectively used. operation UART 1 (SCI) 2 Extended intelligent I/O service function (EI OS) With full-duplex double buffer (8-bit length) Embedded ROM size and types Clock asynchronized or clock synchronized serial (extended MASK ROM : 256 Kbytes / 64 Kbytes / 128 Kbytes I/O serial) can be used. Flash ROM : 128 Kbytes/256 Kbytes External interrupt circuit (8 channels) Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes A module for starting an extended intelligent I/O service (evaluation chip) 2 (EI OS) and generating an external interrupt which is Flash ROM triggered by an external input. Supports automatic programming, Embedded Algorithm Delayed interrupt generation module Write/Erase/Erase-Suspend/Resume commands Generates an interrupt request for switching tasks. A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed 8/10-bit A/D converter (8 channels) boot sector in Flash Memory 8/10-bit resolution can be selectively used. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002- 07696 Rev. *A Revised 2016 November 30MB90540G/545G Series Starting by an external trigger input. Flexible message buffering (mailbox and FIFO buffering can Conversion time : 26.3 s be mixed) FULL-CAN interfaces External bus interface : Maximum address space 16 Mbytes MB90540G series : 2 channels Package: QFP-100, LQFP-100 MB90545G series : 1 channel Conforming to Version 2.0 Part A and Part B Document Number: 002- 07696 Rev. *A Page 2 of 70