CY96345/346 CY96F346/F347/F348 2 F MC-16FX, CY96340 Series, 16-bit Proprietary Microcontroller Datasheet CY96340 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed. Features Can also be used to implement embedded debug support Technology 0.18m CMOS DMA Automatic transfer function independent of CPU, can be assigned CPU freely to resources 2 F MC-16FX CPU Interrupts Up to 56 MHz internal, 17.8 ns instruction cycle time Fast Interrupt processing Optimized instruction set for controller applications (bit, byte, word and long-word data types 23 different addressing modes barrel shift 8 programmable priority levels variety of pointers) Non-Maskable Interrupt (NMI) 8-byte instruction execution queue Timers Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) instructions available Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, System clock 17-bit Sub clock timer) On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop) Watchdog Timer 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency CAN when using ceramic resonator depends on Q-factor). Up to 56 MHz external clock for devices with fast clock input feature Supports CAN protocol version 2.0 part A and B 32-100 kHz subsystem quartz clock ISO16845 certified 100kHz/2MHz internal RC clock for quick and safe startup, oscillator Bit rates up to 1 Mbit/s stop detection, watchdog 32 message objects Clock source selectable from main- and subclock oscillator (part Each message object has its own identifier mask number suffix W) and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals. Programmable FIFO mode (concatenation of message objects) Low Power Consumption - 13 operating modes : (different Run, Sleep, Maskable interrupt Timer modes, Stop mode) Disabled Automatic Retransmission mode for Time Triggered CAN Clock modulator applications Programmable loop-back mode for self-test operation On-chip voltage regulator Internal voltage regulator supports reduced internal MCU voltage, USART offering low EMI and low power consumption figures Full duplex USARTs (SCI/LIN) Low voltage reset Wide range of baud rate settings using a dedicated reload timer Reset is generated when supply voltage is below minimum Special synchronous options for adapting to different synchronous serial protocols Code Security LIN functionality working either as master or slave LIN device Protects ROM content from unintended read-out 2 I C Memory Patch Function Up to 400 kbps Replaces ROM content Master and Slave functionality, 8-bit and 10-bit addressing Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04579 Rev. *B Revised May 31, 2018CY96340 Series Once enabled, can not be disabled other than by reset. A/D converter Level high or level low sensitive SAR-type Pin shared with external interrupt 0. 10-bit resolution Signals interrupt on conversion end, single conversion mode, External bus interface continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer 8-bit or 16-bit bidirectional data Up to 24-bit addresses A/D Converter Reference Voltage switch 6 chip select signals 2 independent positive A/D converter reference voltages available Multiplexed address/data lines Reload Timers Wait state request 16-bit wide External bus master possible 1 2 3 4 5 6 Prescaler with 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock Timing programmable frequency Alarm comparator Event count function Monitors an external voltage and generates an interrupt in case of a Free Running Timers voltage lower or higher than the defined thresholds Signals an interrupt on overflow, supports timer clear upon match with Threshold voltages defined externally or generated internally 1 2 3 4 5 Output Compare (0, 4), Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 6 7 8 Status is readable, interrupts can be masked separately 1/2 , 1/2 ,1/2 of peripheral clock frequency I/O Ports Input Capture Units Virtually all external pins can be used as general purpose I/O 16-bit wide All push-pull outputs (except when used as I2C SDA/SCL line) Signals an interrupt upon external event Bit-wise programmable as input/output or peripheral signal Rising edge, falling edge or rising & falling edge sensitive Bit-wise programmable input enable Output Compare Units Bit-wise programmable input levels: Automotive / CMOS-Schmitt 16-bit wide trigger / TTL (TTL levels not supported by all devices) Signals an interrupt when a match with 16-bit I/O Timer occurs Bit-wise programmable pull-up resistor A pair of compare registers can be used to generate an output signal. Bit-wise programmable output driving strength for EMI optimization Programmable Pulse Generator Packages 16-bit down counter, cycle and duty setting registers 100-pin plastic QFP and LQFP Interrupt at trigger, counter borrow and/or duty match Flash Memory PWM operation and one-shot operation Supports automatic programming, Embedded Algorithm Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as Write/Erase/Erase-Suspend/Resume commands counter clock and Reload timer overflow as clock input A flag indicating completion of the algorithm Can be triggered by software or reload timer Number of erase cycles: 10,000 times Real Time Clock Data retention time: 20 years Can be clocked either from sub oscillator (devices with part number Erase can be performed on each sector individually suffix W), main oscillator or from the RC oscillator Sector protection Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) Flash Security feature to protect the content of the Flash Read/write accessible second/minute/hour registers Low voltage detection during Flash erase Can signal interrupts every half second/second/minute/hour/day Internal clock divider and prescaler provide exact 1s clock External Interrupts Edge sensitive or level sensitive Interrupt mask and pending bit per channel Each available CAN channel RX has an external interrupt for wake-up Selected USART channels SIN have an external interrupt for wake-up Non Maskable Interrupt Disabled after reset Document Number: 002-04579 Rev. *B Page 2 of 111