CYISM560BSXC Infineon

SM560 Spread Spectrum Clock Generator Features Applications 25- to 108-MHz operating frequency range VGA controllers Wide (9) range of spread selections LCD panels and monitors Accepts clock and crystal inputs Printers and multi-function devices (MFP) Low power dissipation Benefits 3.3V = 85 mw (50 MHz) Frequency Spread disable function Peak electromagnetic interference (EMI) reduction by 8 to 16 dB Center Spread modulation Fast time to market Low cycle-to cycle jitter Cost reduction Eight-pin SOIC package Block Diagram Pin Configuration 250 K Xin/ REFERENCE 1 Xin/CLK 1 8 Xout DIVIDER CLK 4 pf PD CP LF VDD 2 7 S0 VSS 3 6 S1 MODULATION CONTROL 8 SSCLK 4 5 SSCC Xout FEEDBACK 8 pF VCO DIVIDER 2 VDD INPUT DIVIDER VSS 3 DECODER 4 SSCLK AND MUX LOGIC 5 6 7 SSCC S1 S0 Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600 Document : 38-07020 Rev. *E Revised June 25, 2004 + Feedback SM560SM560 Pin Definitions Pin Name Type Description 1 Xin/CLK I Clock or Crystal connection input. Refer to Table 1 for input frequency range selection. 2 VDD P Positive power supply. 3 GND P Power supply ground. 4 SSCLK O Modulated clock output. 5 SSCC I Spread Spectrum Clock Control (Enable/Disable) function. SSCG function is enabled when input is high and disabled when input is low. This pin is pulled high internally. 6 S1 I Tri-level Logic input control pin used to select frequency and bandwidth. Frequency/bandwidth selection and Tri-level Logic programming. See Figure 1. 7 S0 I Tri-level Logic input control pin used to select frequency and bandwidth. Frequency/bandwidth selection and Tri-level Logic programming. See Figure 1. 8 Xout O Oscillator output pin connected to crystal. Leave this pin unconnected If an external clock drives Xin/CLK. Functional Description The Cypress SM560 is a Spread Spectrum Clock Generator one of the nine available Frequency Modulation and Spread% (SSCG) IC used for the purpose of reducing Electro Magnetic ranges. Refer to Table 1 for programming details. Interference (EMI) found in todays high-speed digital The SM560 is optimized for SVGA (40 MHz) and XVGA (65 electronic systems. MHz) Controller clocks and also suitable for the applications The SM560 uses a Cypress-proprietary Phase-Locked Loop with the frequency range of 25 to 108 MHz. (PLL) and Spread Spectrum Clock (SSC) technology to A wide range of digitally selectable spread percentages is synthesize and frequency modulate the input frequency of the made possible by using three-level (High, Low and Middle) reference clock. By frequency modulating the clock, the logic at the S0 and S1 digital control inputs. measured EMI at the fundamental and harmonic frequencies The output spread (frequency modulation) is symmetrically of Clock (SSCLK1) is greatly reduced. centered on the input frequency. This reduction in radiated energy can significantly reduce the Spread Spectrum Clock Control (SSCC) function enables or cost of complying with regulatory requirements and time to disables the frequency spread and is provided for easy market without degrading the system performance. comparison of system performance during EMI testing. The SM560 is a very simple and versatile device to use. The The SM560 is available in an eight-pin SOIC package with a 0 frequency and spread% range is selected by programming S0 to 70C operating temperature range. and S1digital inputs. These inputs use three (3) logic states including High (H), Low (L) and Middle (M) logic levels to select Table 1. Frequency and Spread% Selection (Center Spread) 25 54 M Hz (Low Range) Input S1=M S1=M S1=1 S1=0 S1=0 Select the Frequency S0=M S0=0 S0=0 S0=0 S0=M Frequency and Center Spread % (M Hz) (% ) (%) (% ) (% ) (% ) desired and then 25 35 3.8 3.2 2.8 2.3 1.9 set S1, S0 as 35 40 3.5 3.0 2.5 2.1 1.7 indicated. 40 45 3.2 2.8 2.4 1.9 1.6 45 50 3.0 2.6 2.2 1.8 1.5 50 54 2.8 2.4 2.0 1.7 1.4 50 108 M Hz (High Range) Input S1=1 S1=0 S1=1 S1=M Select the Frequency S0=M S0=1 S0=1 S0=1 Frequency and (M Hz) (% ) (%) (% ) (% ) Center Spread % desired and then 50 60 2.5 1.9 1.2 1.0 set S1, S0 as 60 70 2.4 1.8 1.1 0.9 indicated. 70 80 2.3 1.6 1.1 0.9 80 100 2.0 1.4 1.0 0.8 100 108 1.8 1.3 0.8 0.6 Document : 38-07020 Rev. *E Page 2 of 8 + Feedback