System Host CYP15G0201DXB Dual-channel HOTLink II Transceiver Dual-channel HOTLink IITM Transceiver Optional phase-align buffer in transmit path Features Optional elasticity buffer in receive path Second-generation HOTLink technology Dual differential positive ECL (PECL) compatible serial inputs Compliant to multiple standards per channel ESCON, DVB-ASI, Fibre Channel, and Gigabit Ethernet (IEEE 802.3z) Internal DC-restoration CPRI compliant Dual differential PECL-compatible serial outputs per channel 8B/10B encoded or 10-bit unencoded data Source matched for 50- transmission lines No external bias resistors required Dual-channel transceiver operates from 195- to 1500-MBd Signaling-rate controlled edge-rates serial data rate Aggregate throughput of 6 Gbps Compatible with Fiber optic modules Selectable parity check/generate Copper cables Selectable dual-channel bonding option Circuit board traces One 16-bit channels JTAG boundary scan Skew alignment support for multiple bytes of offset Built-in self-test (BIST) for at-speed link testing Selectable I/O clocking options Per-channel link quality indicator MultiFrame receive framer Analog signal detect Bit and byte alignment Digital signal detect Comma or full K28.5 detect Low power 1.8 W at 3.3-V typical Single- or multi-byte framer for byte alignment Low-latency option Single 3.3 V supply Synchronous LVTTL parallel interface 196-ball BGA Internal phase-locked loops (PLLs) with no external PLL Pb-free package components 0.25-m BiCMOS technology Functional Description The CYP15G0201DXB dual-channel HOTLink II transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195- to 1500-MBd per serial link. Figure 1. HOTLink II System Connections 10 10 Serial Links 10 10 10 10 Serial Links 10 10 Backplane or Cabled Connections Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-02058 Rev. *O Revised November 9, 2017 CYP15G0201DXB CYP15G0201DXB System HostCYP15G0201DXB The CYP15G0201DXB operates from 195 to 1500 MBd. completely integrated PLL clock synchronizer, recovers the timing information necessary for data reconstruction. Each The two channels may be combined to allow transport of wide recovered bit-stream is deserialized and framed into characters, buses across significant distances with minimal concern for 8B/10B decoded, and checked for transmission errors. offsets in clock phase or link delay. Each transmit channel Recovered decoded characters are then written to an internal accepts parallel characters in an input register, encodes each Elasticity Buffer, and presented to the destination host system. character for transport, and converts it to serial data. Each The integrated 8B/10B encoder/decoder may be bypassed for receive channel accepts serial data and converts it to parallel systems that present externally encoded or scrambled data at data, decodes the data into characters, and presents these the parallel interface. characters to an Output Register. Figure 1 on page 1 illustrates typical connections between independent host systems and For those systems using buses wider than a single byte, the two corresponding CYP15G0201DXB parts. As a second-generation independent receive paths can be bonded together to allow HOTLink device, the CYP15G0201DXB extends the HOTLink synchronous delivery of data across a two-byte-wide (16-bit) family with enhanced levels of integration and faster data rates, path. while maintaining serial-link compatibility (data, command, and The parallel I/O interface may be configured for numerous forms BIST) with other HOTLink devices. of clocking to provide the highest flexibility in system The transmit (TX) section of the CYP15G0201DXB Dual architecture. In addition to clocking the transmit path interfaces HOTLink II consists of two byte-wide channels that can be from one of multiple sources, the receive interface may be operated independently or bonded to form wider buses. Each configured to present data relative to a recovered clock or to a channel can accept either 8-bit data characters or pre-encoded local reference clock. 10-bit transmission characters. Data characters are passed from Each transmit and receive channel contains independent BIST the Transmit Input Register to an embedded 8B/10B Encoder to pattern generators and checkers. This BIST hardware allows improve their serial transmission characteristics. These encoded at-speed testing of the high-speed serial data paths in each characters are then serialized and output from dual Positive ECL transmit and receive section, and across the interconnecting (PECL) compatible differential transmission-line drivers at a links. bit-rate of either 10 or 20 times the input reference clock. HOTLink II devices are ideal for a variety of applications where The receive (RX) section of the CYP15G0201DXB Dual parallel interfaces can be replaced with high-speed, HOTLink II consists of two byte-wide channels that can be point-to-point serial links. Some applications include operated independently or synchronously bonded for greater interconnecting backplanes on switches, routers, base-stations, bandwidth. Each channel accepts a serial bit-stream from one of servers and video transmission systems. two PECL-compatible differential line receivers and, using a Transceiver Logic Block Diagram x10 x10 x11 x11 Phase Phase Elasticity Elasticity Align Align Buffer Buffer Buffer Buffer Decoder Encoder Decoder Encoder 8B/10B 8B/10B 8B/10B 8B/10B Framer Framer Serializer Deserializer Serializer Deserializer RX TX RX TX Document Number: 38-02058 Rev. *O Page 2 of 53 TXDA 7:0 OUTA1 OUTA2 TXCTA 1:0 INA1 RXDA 7:0 INA2 RXSTA 2:0 OUTB1 TXDB 7:0 TXCTB 1:0 OUTB2 RXDB 7:0 INB1 RXSTB 2:0 INB2