CYP15G0401DXB-BGXI Infineon

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCYP15G0401DXB CYV15G0401DXB Quad HOTLink II Transceiver Internal phase-locked loops (PLLs) with no external PLL Features components Second-generation HOTLink technology Dual differential PECL-compatible serial inputs per channel Compliant to multiple standards Internal DC-restoration ESCON, DVB-ASI, fibre channel and gigabit ethernet Dual differential PECL-compatible serial outputs per channel (IEEE802.3z) Source matched for 50 transmission lines CPRI compliant No external bias resistors required CYV15G0401DXB compliant to SMPTE 259M and Signaling-rate controlled edge-rates SMPTE 292M 8 B/10 B encoded or 10-bit unencoded data Compatible with Fiber-optic modules Quad channel transceiver operates from 195 to 1500 MBaud Copper cables serial data rate Circuit board traces Aggregate throughput of 12 GB per second JTAG boundary scan Selectable parity check/generate Built-in self-test (BIST) for at-speed link testing Selectable multi-channel bonding options Four 8-bit channels Per-channel link quality indicator Two 16-bit channels Analog signal detect One 32-bit channel Digital signal detect N 32-bit channel support (inter-chip) Low power 2.5 W at 3.3 V typical Skew alignment support for multiple bytes of offset Single 3.3 V supply Selectable input/output clocking options 256-ball thermally enhanced BGA MultiFrame receive framer Pb-free package option available Bit and byte alignment Comma or full K28.5 detect 0.25 BiCMOS technology Single- or multi-byte framer for byte alignment Functional Description Low-latency option 1 Synchronous LVTTL parallel interface The CYP(V)15G0401DXB Quad HOTLink II Transceiver is a point-to-point or point-to-multipoint communications Optional elasticity buffer in receive path building block allowing the transfer of data over high-speed Optional phase align buffer in transmit path serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195-to-1500 MBaud per serial link. Figure 1. HOTLink II System Connections 10 10 Serial Links 10 10 10 Serial Links 10 10 10 Serial Links 10 10 10 10 Serial Links 10 Backplane or 10 Cabled 10 Connections 10 Note 1. CYV15G0401DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0401DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-02002 Rev. *P Revised August 18, 2017 System Host CYP(V)15G0401DXB CYP(V)15G0401DXB System Host