CYP15G0403DXB Independent Clock Quad HOTLink II Transceiver Per-channel Link Quality Indicator Features Analog signal detect Second-generation HOTLink technology Digital signal detect Compliant to multiple standards Low-power 3W at 3.3-V typical ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet Single 3.3-V supply (IEEE802.3z) CPRI compliant 256-ball thermally enhanced BGA 8B/10B coded data or 10 bit uncoded data Pb-free package option available Quad channel transceiver operates from 195 to 1500 MBaud 0.25 BiCMOS technology serial data rate Aggregate throughput of up to 12 Gbits/second Functional Description Second-generation HOTLink technology The CYP15G0403DXB Independent Clock Quad Truly independent channels HOTLink II Transceiver is a point-to-point or point-to-multi- Each channel can operate at a different signaling rate point communications building block enabling transfer of data Each channel can transport a different type of data over a variety of high-speed serial links like optical fiber, balanced, and unbalanced copper transmission lines. The Selectable input/output clocking options signaling rate can be anywhere in the range of 195 to Internal phase-locked loops (PLLs) with no external PLL 1500 MBaud per serial link. Each channel operates indepen- components dently with its own reference clock allowing different rates. Each transmit channel accepts parallel characters in an Input Dual differential PECL-compatible serial inputs per channel Register, encodes each character for transport, and then converts it to serial data. Each receive channel accepts serial Internal DC-restoration data and converts it to parallel data, decodes the data into Dual differential PECL-compatible serial outputs per channel characters, and presents these characters to an Output Source matched for 50- transmission lines Register. Figure 1 on page 2 illustrates typical connections between independent host systems and corresponding No external bias resistors required CYP15G0403DXB chips Signaling-rate controlled edge-rates As a second-generation HOTLink device, the MultiFrame Receive Framer provides alignment options CYP15G0403DXB extends the HOTLink family with enhanced Bit and byte alignment levels of integration and faster data rates, while maintaining Comma or Full K28.5 detect serial-link compatibility (data, command, and BIST) with other Single or Multi-byte Framer for byte alignment HOTLink devices. The transmit (TX) section of the Low-latency option CYP15G0403DXB Quad HOTLink II consists of four independent byte-wide channels. Each channel can accept Synchronous LVTTL parallel interface either 8-bit data characters or preencoded 10-bit transmission JTAG boundary scan characters. Data characters may be passed from the Transmit Input Register to an integrated 8B/10B Encoder to improve Built-In Self-Test (BIST) for at-speed link testing their serial transmission characteristics. These encoded characters are then serialized and output from dual Positive Compatible with ECL (PECL) compatible differential transmission-line drivers Fiber-optic modules at a bit-rate of either 10 or 20 times the input reference clock Copper cables for that channel. Circuit board traces . Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-02065 Rev. *J Revised June 9, 2014System Host CYP15G0403DXB Figure 1. HOTLink II System Connections 10 Serial Links 10 10 10 10 10 Serial Links 10 10 Independent Independent CYP15G0403DXB CYP15G0403DXB 10 10 Serial Links 10 10 Backplane or Cabled Connections 10 10 Serial Links 10 10 The receive (RX) section of the CYP15G0403DXB Quad tecture. In addition to clocking the transmit path with a local HOTLink II consists of four independent byte-wide channels. reference clock, the receive interface may also be configured to Each channel accepts a serial bit-stream from one of two present data relative to a recovered clock or to a local reference PECL-compatible differential line receivers, and using a clock. completely integrated Clock and Data Recovery PLL, recovers Each transmit and receive channel contains an independent the timing information necessary for data reconstruction. Each BIST pattern generator and checker. This BIST hardware allows recovered bit-stream is deserialized and framed into characters, at-speed testing of the high-speed serial data paths in each 8B/10B decoded, and checked for transmission errors. transmit and receive section, and across the interconnecting Recovered decoded characters are then written to an internal links. Elasticity Buffer, and presented to the destination host system. The CYP15G0403DXB is ideal for port applications where The integrated 8B/10B encoder/decoder may be bypassed for different data rates and serial interface standards are necessary systems that present externally encoded or scrambled data at for each channel. Some applications include multi-protocol the parallel interface. routers, aggregation equipment, and switches. The parallel I/O interface may be configured for numerous forms of clocking to provide the highest flexibility in system archi- Document : 38-02065 Rev. *J Page 2 of 49 System Host