MB96610 Series 2 F MC-16FX , 16-bit Proprietary Microcontroller 2 MB96610 series is based on Cypress advanced F MC-16FX architecture (16-bit with instruction pipeline 2 for RISC-like performance). The CPU uses the same instruction set as the established F MC-16LX family 2 2 2 thus allowing for easy migration of F MC-16LX Software to the new F MC-16FX products. F MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time.For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. Features Technology On-chip voltage regulator 0.18m CMOS Internal voltage regulator supports a wide MCU supply voltage range (Min=2.7V), offering low power consumption CPU 2 F MC-16FX CPU Low voltage detection function Optimized instruction set for controller applications Reset is generated when supply voltage falls below (bit, byte, word and long-word data types, 23 different programmable reference voltage addressing modes, barrel shift, variety of pointers) 8-byte instruction queue Code Security Signed multiply (16-bit 16-bit) and divide Protects Flash Memory content from unintended (32-bit/16-bit) instructions available read-out System clock DMA On-chip PLL clock multiplier ( 1 to 8, 1 when PLL Automatic transfer function independent of CPU, can stop) be assigned freely to resources 4MHz to 8MHz crystal oscillator (maximum frequency when using ceramic resonator Interrupts depends on Q-factor) Fast Interrupt processing Up to 8MHz external clock for devices with fast clock 8 programmable priority levels input feature Non-Maskable Interrupt (NMI) 32.768kHz subsystem quartz clock 100kHz/2MHz internal RC clock for quick and safe CAN startup, clock stop detection function, watchdog Supports CAN protocol version 2.0 part A and B Clock source selectable from mainclock oscillator, ISO16845 certified subclock oscillator and on-chip RC oscillator, independently for CPU and 2 clock domains of Bit rates up to 1Mbps peripherals 32 message objects The subclock oscillator is enabled by the Boot ROM Each message object has its own identifier mask program controlled by a configuration marker after a Programmable FIFO mode (concatenation of Power or External reset message objects) Low Power Consumption - 13 operating modes Maskable interrupt (different Run, Sleep, Timer, Stop modes) Disabled Automatic Retransmission mode for Time Triggered CAN applications Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04709 Rev *A Revised March 1, 2016 MB96610 Series Programmable loop-back mode for self-test operation Output Compare Units 16-bit wide USART Signals an interrupt when a match with Free-running Full duplex USARTs (SCI/LIN) Timer occurs Wide range of baud rate settings using a dedicated A pair of compare registers can be used to generate reload timer an output signal Special synchronous options for adapting to different synchronous serial protocols Programmable Pulse Generator LIN functionality working either as master or slave 16-bit down counter, cycle and duty setting registers LIN device Can be used as 2 8-bit PPG Extended support for LIN-Protocol to reduce interrupt Interrupt at trigger, counter borrow and/or duty match load PWM operation and one-shot operation A/D converter Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected SAR-type Reload timer underflow as clock input 8/10-bit resolution Can be triggered by software or reload timer Signals interrupt on conversion end, single Can trigger ADC conversion conversion mode, continuous conversion mode, stop conversion mode, activation by software, Timing point capture external trigger, reload timers and PPGs Quadrature Position/Revolution Counter Range Comparator Function (QPRC) Source Clock Timers Up/down count mode, Phase difference count mode, Three independent clock timers (23-bit RC clock Count mode with direction timer, 23-bit Main clock timer, 17-bit Sub clock timer) 16-bit position counter 16-bit revolution counter Hardware Watchdog Timer Two 16-bit compare registers with interrupt Hardware watchdog timer is active after reset Detection edge of the three external event input pins Window function of Watchdog Timer is used to select AIN, BIN and ZIN is configurable the lower window limit of the watchdog interval Real Time Clock Reload Timers Operational on main oscillation (4MHz), sub 16-bit wide oscillation (32kHz) or RC oscillation (100kHz/2MHz) 1 2 3 4 5 6 Prescaler with 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of Capable to correct oscillation deviation of Sub clock peripheral clock frequency or RC oscillator clock (clock calibration) Event count function Read/write accessible second/minute/hour registers Free-Running Timers Can signal interrupts every half second/second/minute/hour/day Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4) Internal clock divider and prescaler provide exact 1s 1 2 3 4 5 6 7 clock Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 8 1/2 of peripheral clock frequency External Interrupts Input Capture Units Edge or Level sensitive 16-bit wide Interrupt mask bit per channel Signals an interrupt upon external event Each available CAN channel RX has an external interrupt for wake-up Rising edge, Falling edge or Both (rising & falling) edges sensitive Selected USART channels SIN have an external interrupt for wake-up Document Number: 002-04709 Rev *A Page 2 of 64