MB96F6A5R/A MB96F6A6R 2 F MC-16FX MB966A0 Series 16-bit Proprietary Microcontroller Datasheet 2 MB966A0 series is based on Cypresss advanced F MC-16FX architecture (16-bit with instruction pipeline for RISC-like performance). 2 The CPU uses the same instruction set as the established F2MC-16LX family thus allowing for easy migration of F MC-16LX 2 2 Software to the new F MC-16FX products. F MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. Features Technology On-chip voltage regulator 0.18 m CMOS Internal voltage regulator supports a wide MCU supply voltage range (Min=2.7V), offering low power consumption CPU Low voltage detection function 2 F MC-16FX CPU Reset is generated when supply voltage falls below Optimized instruction set for controller applications programmable reference voltage (bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers) Code Security 8-byte instruction queue Protects Flash Memory content from unintended read-out Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) instructions available DMA Automatic transfer function independent of CPU, can be System clock assigned freely to resources On-chip PLL clock multiplier ( 1 to 8, 1 when PLL stop) Interrupts 4MHz to 8MHz crystal oscillator (maximum frequency when using ceramic resonator Fast Interrupt processing depends on Q-factor) 8 programmable priority levels Up to 8MHz external clock for devices with fast clock input feature Non-Maskable Interrupt (NMI) 32.768kHz subsystem quartz clock CAN 100kHz/2MHz internal RC clock for quick and safe startup, Supports CAN protocol version 2.0 part A and B clock stop detection function, watchdog ISO16845 certified Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator, independently for CPU Bit rates up to 1Mbps and 2 clock domains of peripherals 32 message objects The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after a Power or Each message object has its own identifier mask External reset Programmable FIFO mode (concatenation of message Low Power Consumption - 13 operating modes (different objects) Run, Sleep, Timer, Stop modes) Maskable interrupt Disabled Automatic Retransmission mode for Time Triggered CAN applications Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04715 Rev.*A Revised May 25, 2016 MB966A0 Series Programmable loop-back mode for self-test operation Signals an interrupt upon external event Rising edge, Falling edge or Both (rising & falling) edges USART sensitive Full duplex USARTs (SCI/LIN) Output Compare Units Wide range of baud rate settings using a dedicated reload timer 16-bit wide Special synchronous options for adapting to different Signals an interrupt when a match with Free-running Timer synchronous serial protocols occurs LIN functionality working either as master or slave LIN device A pair of compare registers can be used to generate an output signal Extended support for LIN-Protocol to reduce interrupt load Programmable Pulse Generator 2 I C 16-bit down counter, cycle and duty setting registers Up to 400kbps Can be used as 2 8-bit PPG Master and Slave functionality, 7-bit and 10-bit addressing Interrupt at trigger, counter borrow and/or duty match A/D converter PWM operation and one-shot operation SAR-type Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected Reload timer underflow as 8/10-bit resolution clock input Signals interrupt on conversion end, single conversion mode, Can be triggered by software or reload timer continuous conversion mode, stop conversion mode, activation by software, external Can trigger ADC conversion trigger, reload timers and PPGs Timing point capture Range Comparator Function Start delay Scan Disable Function Stepping Motor Controller ADC Pulse Detection Function Stepping Motor Controller with integrated high current output Source Clock Timers drivers Three independent clock timers (23-bit RC clock timer, 23-bit Four high current outputs for each channel Main clock timer, 17-bit Sub clock timer) Two synchronized 8/10-bit PWMs per channel Hardware Watchdog Timer Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock Hardware watchdog timer is active after reset Dedicated power supply for high current output drivers Window function of Watchdog Timer is used to select the lower window limit of the watchdog interval LCD Controller Reload Timers LCD controller with up to 4COM 44SEG 16-bit wide Internal or external voltage generation 1 2 3 4 5 6 Prescaler with 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral Duty cycle: Selectable from options: 1/2, 1/3 and 1/4 clock frequency Fixed 1/3 bias Event count function Programmable frame period Free-Running Timers Clock source selectable from four options (main clock, peripheral clock, subclock or RC oscillator clock) Signals an interrupt on overflow, supports timer clear upon Internal divider resistors or external divider resistors match with Output Compare (0, 4) 1 2 3 4 5 6 7 8 On-chip data memory for display Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock frequency LCD display can be operated in Timer Mode Blank display: selectable Input Capture Units 16-bit wide Document Number: 002-04715 Rev.*A Page 2 of 75