MB966B0 Series 2 F MC-16FX 16-Bit Microcontroller 2 MB966B0 series is based on Cypress advanced F MC-16FX architecture (16-bit with instruction pipeline for RISC-like performance). 2 2 The CPU uses the same instruction set as the established F MC-16LX family thus allowing for easy migration of F MC-16LX 2 Software to the new F MC-16FX products. 2 F MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. Features Technology Interrupts Fast Interrupt processing 0.18 m CMOS 8 programmable priority levels CPU Non-Maskable Interrupt (NMI) 2 F MC-16FX CPU CAN Optimized instruction set for controller applications Supports CAN protocol version 2.0 part A and B (bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers) ISO16845 certified 8-byte instruction queue Bit rates up to 1Mbps Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) 32 message objects instructions available Each message object has its own identifier mask Programmable FIFO mode (concatenation of message System clock objects) On-chip PLL clock multiplier ( 1 to 8, 1 when PLL stop) Maskable interrupt 4MHz to 8MHz crystal oscillator Disabled Automatic Retransmission mode for Time (maximum frequency when using ceramic resonator Triggered CAN applications depends on Q-factor) Programmable loop-back mode for self-test operation Up to 8MHz external clock for devices with fast clock input feature USART 32.768kHz subsystem quartz clock Full duplex USARTs (SCI/LIN) 100kHz/2MHz internal RC clock for quick and safe startup, Wide range of baud rate settings using a dedicated reload clock stop detection function, watchdog timer Clock source selectable from mainclock oscillator, subclock Special synchronous options for adapting to different oscillator and on-chip RC oscillator, independently for CPU synchronous serial protocols and 2 clock domains of peripherals LIN functionality working either as master or slave LIN The subclock oscillator is enabled by the Boot ROM device program controlled by a configuration marker after a Power Extended support for LIN-Protocol with 16-byte FIFO for or External reset selected channels to reduce interrupt load Low Power Consumption - 13 operating modes (different 2 Run, Sleep, Timer, Stop modes) I C Up to 400kbps On-chip voltage regulator Master and Slave functionality, 7-bit and 10-bit addressing Internal voltage regulator supports a wide MCU supply voltage range (Min=2.7V), offering low power consumption A/D converter SAR-type Low voltage detection function 8/10-bit resolution Reset is generated when supply voltage falls below Signals interrupt on conversion end, single conversion programmable reference voltage mode, continuous conversion mode, stop conversion mode, activation by software, external Code Security trigger, reload timers and PPGs Protects Flash Memory content from unintended read-out Range Comparator Function Scan Disable Function DMA ADC Pulse Detection Function Automatic transfer function independent of CPU, can be assigned freely to resources Source Clock Timers Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04721 Rev.*A Revised March 3, 2016 MB966B0 Series All SEG, COM and V pins can be switched between Hardware Watchdog Timer general and specialized purposes Hardware watchdog timer is active after reset Window function of Watchdog Timer is used to select the Sound Generator lower window limit of the watchdog interval 8-bit PWM signal is mixed with tone frequency from 16-bit reload counter Reload Timers PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of 16-bit wide 1 2 3 4 5 6 peripheral clock Prescaler with 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock frequency Real Time Clock Event count function Operational on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz) Free-Running Timers Capable to correct oscillation deviation of Sub clock or RC Signals an interrupt on overflow, supports timer clear upon oscillator clock (clock calibration) match with Output Compare (0) 1 2 3 4 5 6 7 8 Read/write accessible second/minute/hour registers Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 Can signal interrupts every half of peripheral clock frequency second/second/minute/hour/day Input Capture Units Internal clock divider and prescaler provide exact 1s clock 16-bit wide External Interrupts Signals an interrupt upon external event Edge or Level sensitive Rising edge, Falling edge or Both (rising & falling) edges Interrupt mask bit per channel sensitive Each available CAN channel RX has an external interrupt Output Compare Units for wake-up 16-bit wide Selected USART channels SIN have an external interrupt for wake-up Signals an interrupt when a match with Free-running Timer occurs Non Maskable Interrupt A pair of compare registers can be used to generate an Disabled after reset, can be enabled by Boot-ROM output signal depending on ROM configuration block Programmable Pulse Generator Once enabled, cannot be disabled other than by reset 16-bit down counter, cycle and duty setting registers High or Low level sensitive Can be used as 2 8-bit PPG Pin shared with external interrupt 0 Interrupt at trigger, counter borrow and/or duty match I/O Ports PWM operation and one-shot operation Most of the external pins can be used as general purpose Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral I/O clock as counter clock or of selected Reload timer 2 All push-pull outputs (except when used as I C SDA/SCL underflow as clock input line) Can be triggered by software or reload timer Bit-wise programmable as input/output or peripheral signal Can trigger ADC conversion Bit-wise programmable input enable Timing point capture One input level per GPIO-pin (either Automotive or CMOS Start delay hysteresis) Bit-wise programmable pull-up resistor Quadrature Position/Revolution Counter (QPRC) Some pins offer high current output capability for LED Up/down count mode, Phase difference count mode, driving. Count mode with direction 16-bit position counter Built-in On Chip Debugger (OCD) 16-bit revolution counter One-wire debug tool interface Two 16-bit compare registers with interrupt Break function: Detection edge of the three external event input pins AIN, Hardware break: 6 points (shared with code event) BIN and ZIN is configurable Software break: 4096 points LCD Controller Event function LCD controller with up to 4COM 36SEG Code event: 6 points (shared with hardware break) Internal or external voltage generation Data event: 6 points Duty cycle: Selectable from options: 1/2, 1/3 and 1/4 Event sequencer: 2 levels + reset Fixed 1/3 bias Execution time measurement function Programmable frame period Trace function: 42 branches Clock source selectable from four options (main clock, Security function peripheral clock, subclock or RC oscillator clock) Internal divider resistors or external divider resistors On-chip data memory for display LCD display can be operated in Timer Mode Blank display: selectable Document Number: 002-04721 Rev.*A Page 2 of 74