S25FL064L 64-Mbit (8-Mbyte) 3.0 V FL-L SPI Flash Memory General Description The Cypress FL-L Family devices are Flash Nonvolatile Memory products using: Floating Gate technology 65-nm process lithography The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO), and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4 KB sector, 32 KB half block sector, 64 KB block sector, or entire chip erase. By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically. The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power. These memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing re-programmable data. Features Serial Peripheral Interface (SPI) with Multi-I/O Four security regions of 256-bytes each outside the main Flash Clock polarity and phase modes 0 and 3 array Double Data Rate (DDR) option Legacy block protection: Block range Quad peripheral interface (QPI) option Individual and region protection Extended addressing: 24- or 32-bit address options Individual block lock: Volatile individual sector/block Serial command subset and footprint compatible with S25FL-A, Pointer region: Nonvolatile sector/block range S25FL1-K, S25FL-P, S25FL-S, and S25FS-S SPI families Power supply Lock-down, password, or permanent protection Multi I/O command subset and footprint compatible with S25FL-P, of security regions 2 and 3 and pointer region S25FL-S and S25FS-S SPI families Technology Read 65-nm Floating Gate technology Commands: Normal, Fast, Dual I/O, Quad I/O, DualO, QuadO, Single Supply Voltage with CMOS I/O DDR Quad I/O 2.7 V to 3.6 V Modes: Burst wrap, Continuous (XIP), QPI Temperature Range / Grade Serial flash discoverable parameters (SFDP) for configuration Industrial (40C to +85C) information Industrial Plus (40C to +105C) Program Architecture Automotive, AEC-Q100 Grade 3 (40C to +85C) 256-Bytes page programming buffer Automotive, AEC-Q100 Grade 2 (40C to +105C) Program suspend and resume Automotive, AEC-Q100 Grade 1 (40C to +125C) Erase Architecture Packages (All Pb-free) Uniform 4 KB sector erase 8-lead SOIC 208 mil (SOC008) Uniform 32 KB half block erase 16-lead SOIC 300 mil (SO3016) Uniform 64 KB block erase USON 4 4 mm (UNF008) Chip erase WSON 5 x 6 mm (WND008) Erase suspend and resume BGA-24 6 8 mm 100,000 Program-Erase Cycles, minimum 5 5 ball (FAB024) footprint 20 Year Data Retention, minimum 4 6 ball (FAC024) footprint Security Features Known good die and known tested die Status and configuration Register protection Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-12878 Rev. *E Revised July 11, 2018S25FL064L Performance Summary Maximum Read Rates SDR Command Clock Rate (MHz) MBps Read 50 6.25 Fast Read 108 13.5 Dual Read 108 27 Quad Read 108 54 Maximum Read Rates DDR Command Clock Rate (MHz) MBps DDR Quad Read 54 54 Typical Program and Erase Rates Operation KBytes/s Page Programming 569 4 KBytes Sector Erase 61 32 KBytes Half Block Erase 106 64 KBytes Block Erase 142 Typical Current Consumption Operation Typical Current Unit Read 50 MHz 10 mA Fast Read 5MHz 10 mA Fast Read 10 MHz 10 mA Fast Read 20 MHz 10 mA Fast Read 50 MHz 15 mA Fast Read 108 MHz 25 mA Quad I/O / QPI Read 108 MHz 25 mA Quad I/O / QPI DDR Read 33MHz 15 mA Quad I/O / QPI DDR Read 54MHz 30 mA Program 40 mA Erase 40 mA Standby SPI 20 A Standby QPI 60 A Deep Power Down 2A Document Number: 002-12878 Rev. *E Page 2 of 152