S25FL064P 64-Mbit 3.0 V SPI Flash Memory This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede S25FL064P. These are the factory-recommended migration paths. Please refer to the S25FL-L Family data sheets for specifications and ordering information. Distinctive Characteristics CFI (Common Flash Interface) compliant: allows host system Architectural Advantages to identify and accommodate multiple flash devices Single power supply operation Process technology Full voltage range: 2.7 to 3.6V read and write operations Manufactured on 90-nm MirrorBit process technology Memory architecture Package option Uniform 64-kB sectors Industry Standard Pinouts Top or bottom parameter block (Two 64-kB sectors (top 16-pin SO package (300 mils) or bottom) broken down into sixteen 4-kB sub-sectors each) 8-contact WSON package (6 8 mm) 256-byte page size 24-ball BGA package (6 8 mm), 5 5 pin configuration Backward compatible with the S25FL064A device 24-ball BGA package (6 8 mm), 6 4 pin configuration Program Performance Characteristics Page Program (up to 256 bytes) in 1.5 ms (typical) Speed Program operations are on a page by page basis Normal READ (Serial): 40 MHz clock rate Accelerated programming mode via 9V W /ACC pin FAST READ (Serial): 104 MHz clock rate (maximum) Quad Page Programming DUAL I/O FAST READ: 80 MHz clock rate or Erase 20 MB/s effective data rate Bulk erase function QUAD I/O FAST READ: 80 MHz clock rate or Sector erase (SE) command (D8h) for 64-kB sectors 40 MB/s effective data rate Sub-sector erase (P4E) command (20h) for 4-kB sectors Power saving standby mode Sub-sector erase (P8E) command (40h) for 8-kB sectors Standby Mode 80 A (typical) Cycling endurance Deep Power-Down Mode 3 A (typical) 100,000 cycles per sector typical Data retention Memory Protection Features 20 years typical Memory protection Device ID W /ACC pin works in conjunction with Status Register Bits to protect specified memory areas JEDEC standard two-byte electronic signature Status Register Block Protection bits (BP2, BP1, BP0) in RES command one-byte electronic signature for backward status register configure parts of memory as read-only compatibility One time programmable (OTP) area for permanent, secure Software Features identification can be programmed and locked at the factory SPI Bus Compatible Serial Interface or by the customer Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00649 Rev. *J Revised May 22, 2017 Not Recommended for New DesignsS25FL064P General Description The S25FL064P is a 3.0 Volt (2.7V to 3.6V), single-power-supply flash memory device. The device consists of 128 uniform 64 kB sectors with the two (Top or Bottom) 64 kB sectors further split up into thirty-two 4 kB sub sectors. The S25FL064P device is fully backward compatible with the S25FL064A device. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3.0-volt V supply. CC The S25FL064P device adds the following high-performance features using 5 new instructions: Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz Quad Output Read using SI, SO, W /ACC and HOLD pins as output pins at a clock rate of up to 80 MHz Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up to 80 MHz Quad I/O High Performance Read using SI, SO, W /ACC and HOLD pins as input and output pins at a clock rate of up to 80 MHz Quad Page Programming using SI, SO, W /ACC and HOLD pins as input pins to program data at a clock rate of up to 80 MHz The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands. Each device requires only a 3.0-volt power supply (2.7V to 3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device requires a high voltage supply to the W /ACC pin to enable the Accelerated Programming mode. The S25FL064P device also offers a One-Time Programmable area (OTP) of up to 128-bits (16 bytes) for permanent secure identification and an additional 490 bytes of OTP space for other use. This OTP area can be programmed or read using the OTPP or OTPR instructions. Document Number: 002-00649 Rev. *J Page 2 of 63 Not Recommended for New Designs