S25FL127SABBHVC00 Infineon

S25FL127S 128-Mbit (16 Mbyte) 3.0 V SPI Flash Memory Features CMOS 3.0 Volt Core Cycling Endurance Density 100,000 Program-Erase Cycles per sector, minimum 128 Mbits (16 Mbytes) Data Retention Serial Peripheral Interface (SPI) with Multi-I/O 20 Year Data Retention, minimum SPI Clock polarity and phase modes 0 and 3 Security features Extended Addressing: 24- or 32-bit address options One Time Program (OTP) array of 1024 bytes Serial Command set and footprint compatible with Block Protection: S25FL-A, Status Register bits to control protection against S25FL-K, and S25FL-P SPI families program or erase of a contiguous range of sectors. Multi I/O Command set and footprint compatible with Hardware and software control options S25FL-P SPI family Advanced Sector Protection (ASP) READ Commands Individual sector protection controlled by boot code or Normal, Fast, Dual, Quad password AutoBoot - power up or reset and execute a Normal or Cypress 65 nm MirrorBit Technology with Eclipse Quad read command automatically at a preselected Architecture address Supply Voltage: 2.7V to 3.6V Common Flash Interface (CFI) data for configuration Temperature Range: information. Industrial (-40C to +85C) Programming (0.8 Mbytes/s) Industrial Plus (-40C to +105C) 256- or 512-byte Page Programming buffer options Automotive AEC-Q100 Grade 3 (-40C to +85C) Quad-Input Page Programming (QPP) for slow clock Automotive AEC-Q100 Grade 2 (-40C to +105C) systems Packages (all Pb-free) Automatic ECC -internal hardware Error Correction Code 8-lead SOIC (208 mil) generation with single bit error correction 16-lead SOIC (300 mil) Erase (0.5 Mbytes/s) 8-contact WSON 6 x 5 mm Hybrid sector size option - physical set of sixteen 4-kbyte BGA-24 6 x 8 mm sectors at top or bottom of address space with all 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint remaining sectors of 64 kbytes options Uniform sector option - always erase 256-kbyte blocks for Known Good Die and Known Tested Die software compatibility with higher density and future devices. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98282 Rev. *I Revised June 08, 2017S25FL127S Performance Summary Maximum Read Rates Current Consumption Clock Rate Operation Current (mA) Command Mbytes/s (MHz) Serial Read 50 MHz 16 (max) Read 50 6.25 Serial Read 108 MHz 24 (max) Fast Read 108 13.5 Quad Read 108 MHz 47 (max) Dual Read 108 27 Program 50 (max) Quad Read 108 54 Erase 50 (max) Standby 0.07 (typ) Typical Program and Erase Rates Operation kbytes/s Page Programming (256-byte page buffer) 650 Page Programming (512-byte page buffer) 800 4-kbyte Physical Sector Erase (Hybrid 30 Sector Option) 64-kbyte Physical Sector Erase (Hybrid 500 Sector Option) 256-kbyte Logical Sector Erase (Uniform 500 Sector Option) Document Number: 001-98282 Rev. *I Page 3 of 142