S25FL128P 128-Mbit, 3.0 V Flash Memory This product is not recommended for new and current designs. For new and current designs, S25FL128S supersedes S25FL128P. This is the factory-recommended migration path. Please refer to the S25FL128S data sheet for specifications and ordering information. Distinctive Characteristics Process Technology Architectural Advantages Manufactured on 0.09 m MirrorBit process technology Single power supply operation Package Option Full voltage range: 2.7V to 3.6V read and program operations Industry Standard Pinouts Memory Architecture 16-pin SO package (300 mils) 128Mb uniform 256 KB sector product 8-Contact WSON Package (6 x 8 mm) 128Mb uniform 64 KB sector product Program Performance Characteristics Page Program (up to 256 bytes) in 1.5 ms (typical) Speed Faster program time in Accelerated Programming mode 104 MHz clock rate (maximum) (8.5 V9.5 V on WP/ACC) in 1.2 ms (typical) Power Saving Standby Mode Erase Standby Mode 200 A (max) 2 s typical 256 KB sector erase time Deep Power Down Mode 3 A (typical) 0.5 s typical 64 KB sector erase time 128 s typical bulk erase time Memory Protection Features Sector erase (SE) command (D8h) for 256 KB sectors (20h or D8h) for 64KB sectors Memory Protection Bulk erase command (C7h) for 256 KB sectors (60h or C7h) for WP /ACC pin works in conjunction with Status Register Bits to 64KB sectors protect specified memory areas 256 KB uniform sector product: Cycling Endurance Status Register Block Protection bits (BP2, BP1, BP0) in status 100,000 cycles per sector typical register configure parts of memory as read-only. Data Retention 64KB uniform sector product: 20 years typical Status Register Block Protection bits (BP3, BP2, BP1, BP0) in Device ID status register configure parts of memory as read-only RDID (9Fh), READ ID (90h) and RES (ABh) commands to read manufacturer and device ID information Software Features RES command one-byte electronic signature for backward SPI Bus Compatible Serial Interface compatibility Hardware Features x8 Parallel Programming Mode (for 16-pin SO package only) General Description The S25FL128P is a 3.0 Volt (2.7V to 3.6V), single-power-supply Flash memory device. The device consists of 64 sectors of 256 KB memory, or 256 sectors of 64 KB memory. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3.0 volt V supply. CC The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands. Each device requires only a 3.0 volt power supply (2.7V to 3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device requires a high voltage supply to WP /ACC pin for the Accelerated Programming mode. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00646 Rev. *M Revised April 27, 2017S25FL128P Contents Distinctive Characteristics .................................................. 2 18. Test Conditions........................................................... 37 General Description ............................................................. 2 19. AC Characteristics...................................................... 38 19.1 Capacitance.................................................................. 39 1. Block Diagram.............................................................. 4 20. Physical Dimensions.................................................. 41 2. Connection Diagrams.................................................. 5 20.1 SO3 016 wide 16-pin Plastic Small Outline 3. Input/Output Descriptions........................................... 6 Package (300-mil Body Width) .....................................41 20.2 WNF008 WSON 8-contact (6 x 8 mm) No-Lead 4. Logic Symbol ............................................................... 6 Package ........................................................................42 5. Ordering Information................................................... 7 21. Revision History.......................................................... 43 5.1 Valid Combinations........................................................ 7 6. SPI Modes..................................................................... 8 7. Device Operations ....................................................... 9 7.1 Byte or Page Programming............................................ 9 7.2 Sector Erase / Bulk Erase.............................................. 9 7.3 Monitoring Write Operations Using the Status Register 9 7.4 Active Power and Standby Power Modes...................... 9 7.5 Status Register .............................................................. 9 7.6 Data Protection Modes .................................................. 9 7.7 Hold Mode (HOLD ) .................................................... 11 8. Sector Address Table ................................................ 11 9. Parallel Mode (for 16-pin SO package only) ............ 15 10. Accelerated Programming Operation ...................... 15 11. Command Definitions................................................ 16 11.1 Read Data Bytes (READ: 03h) .................................... 16 11.2 Read Data Bytes at Higher Speed (FAST READ: 0Bh) 17 11.3 Read Identification (RDID: 9Fh)................................... 18 11.4 Read Manufacturer and Device ID (READ ID: 90h) 19 11.5 Write Enable (WREN: 06h).......................................... 20 11.6 Write Disable (WRDI: 04h)........................................... 21 11.7 Read Status Register (RDSR: 05h) ............................. 21 11.8 Write Status Register (WRSR: 01h)............................. 24 11.9 Page Program (PP: 02h).............................................. 25 11.10Sector Erase (SE: 20h, D8h) ....................................... 26 11.11Bulk Erase (BE: C7h, 60h) .......................................... 27 11.12Deep Power Down (DP: B9h)...................................... 28 11.13Release from Deep Power Down (RES: ABh) ................................................................. 29 11.14Release from Deep Power Down and Read Electronic Signature (RES: ABh) ........................ 29 11.15Command Definitions .................................................. 31 12. Program Acceleration via WP /ACC pin.................. 32 13. Power-up and Power-down....................................... 33 14. Initial Delivery State................................................... 35 15. Absolute Maximum Ratings...................................... 35 16. Operating Ranges...................................................... 36 17. DC Characteristics..................................................... 36 Document Number: 002-00646 Rev. *M Page 3 of 45