S25FL128S/S25FL256S 128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte) 3.0V SPI Flash Memory Features CMOS 3.0 Volt Core with Versatile I/O Data Retention 20 Year Data Retention Serial Peripheral Interface (SPI) with Multi-I/O SPI Clock polarity and phase modes 0 and 3 Security features Double Data Rate (DDR) option One Time Program (OTP) array of 1024 bytes Extended Addressing: 24- or 32-bit address options Block Protection: Serial Command set and footprint compatible with S25FL-A, Status Register bits to control protection against program or erase S25FL-K, and S25FL-P SPI families of a contiguous range of sectors. Hardware and software control options Multi I/O Command set and footprint compatible with S25FL-P SPI family Advanced Sector Protection (ASP) Individual sector protection controlled by boot code or password READ Commands Cypress 65 nm MirrorBit Technology with Eclipse Architecture Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR AutoBoot - power up or reset and execute a Normal or Quad read Core Supply Voltage: 2.7V to 3.6V command automatically at a preselected address I/O Supply Voltage: 1.65V to 3.6V Common Flash Interface (CFI) data for configuration information. SO16 and FBGA packages Programming (1.5 Mbytes/s) Temperature Range / Grade: 256 or 512 Byte Page Programming buffer options Industrial (-40C to +85C) Quad-Input Page Programming (QPP) for slow clock systems Industrial Plus (-40C to +105C) Automatic ECC -internal hardware Error Correction Code Extended (-40C to +125C) generation with single bit error correction Automotive AEC-Q100 Grade 3 (-40C to +85C) Erase (0.5 to 0.65 Mbytes/s) Automotive AEC-Q100 Grade 2 (-40C to +105C) Hybrid sector size option - physical set of thirty two 4-kbyte sectors Automotive AEC-Q100 Grade 1 (-40C to +125C) at top or bottom of address space with all remaining sectors of Packages (all Pb-free) 64 kbytes, for compatibility with prior generation S25FL devices 16-lead SOIC (300 mil) Uniform sector option - always erase 256-kbyte blocks for software WSON 6 x 8 mm compatibility with higher density and future devices. BGA-24 6 x 8 mm Cycling Endurance 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint options 100,000 Program-Erase Cycles Known Good Die and Known Tested Die Logic Block Diagram CS SRAM SCK MirrorBit Array SI/IO0 SO/IO1 Y Decoders I/O Data Latch WP /IO2 Control Logic HOLD /IO3 Data Path RESET Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98283 Rev. *J Revised September 22, 2016 X DecodersS25FL128S/S25FL256S Performance Summary Maximum Read Rates with the Same Core and I/O Voltage (V = V = 2.7V to 3.6V) IO CC Command Clock Rate (MHz) Mbytes/s Read 50 6.25 Fast Read 133 16.6 Dual Read 104 26 Quad Read 104 52 Maximum Read Rates with Lower I/O Voltage (V = 1.65V to 2.7V, V = 2.7V to 3.6V) IO CC Command Clock Rate (MHz) Mbytes/s Read 50 6.25 Fast Read 66 8.25 Dual Read 66 16.5 Quad Read 66 33 Maximum Read Rates DDR (V = V = 3V to 3.6V) IO CC Command Clock Rate (MHz) Mbytes/s Fast Read DDR 80 20 Dual Read DDR 80 40 Quad Read DDR 80 80 Typical Program and Erase Rates Operation kbytes/s Page Programming (256-byte page buffer - Hybrid Sector Option) 1000 Page Programming (512-byte page buffer - Uniform Sector Option) 1500 4-kbyte Physical Sector Erase (Hybrid Sector Option) 30 64-kbyte Physical Sector Erase (Hybrid Sector Option) 500 256-kbyte Logical Sector Erase (Uniform Sector Option) 500 Current Consumption Operation Current (mA) Serial Read 50 MHz 16 (max) Serial Read 133 MHz 33 (max) Quad Read 104 MHz 61 (max) Quad DDR Read 80 MHz 90 (max) Program 100 (max) Erase 100 (max) Standby 0.07 (typ) Document Number: 001-98283 Rev. *J Page 2 of 149