S25FL128S/S25FL256S 128 Mb (16 MB)/256 Mb (32 MB) 3.0V SPI Flash Memory Features CMOS 3.0 Volt Core with Versatile I/O Data Retention 20 Year Data Retention, minimum SPI with Multi-I/O Security features SPI Clock polarity and phase modes 0 and 3 DDR option OTP array of 1024 bytes Extended Addressing: 24- or 32-bit address options Block Protection: Serial Command set and footprint compatible with Status Register bits to control protection against program S25FL-A, S25FL-K, and S25FL-P SPI families or erase of a contiguous range of sectors. Multi I/O Command set and footprint compatible with Hardware and software control options S25FL-P SPI family Advanced Sector Protection (ASP) READ Commands Individual sector protection controlled by boot code or password Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR AutoBoot - power up or reset and execute a Normal or Quad Cypress 65 nm MirrorBit Technology with Eclipse read command automatically at a preselected address Architecture Common Flash Interface (CFI) data for configuration infor- mation. Core Supply Voltage: 2.7V to 3.6V Programming (1.5 MBps) I/O Supply Voltage: 1.65V to 3.6V 256 or 512 Byte Page Programming buffer options SO16 and FBGA packages Quad-Input Page Programming (QPP) for slow clock sys- Temperature Range / Grade: tems Industrial ( 40C to +85C) Automatic ECC-internal hardware Error Correction Code generation with single bit error correction Industrial Plus ( 40C to +105C) Automotive AEC-Q100 Grade 3 ( 40C to +85C) Erase (0.5 to 0.65 MBps) Automotive AEC-Q100 Grade 2 ( 40C to +105C) Hybrid sector size option - physical set of thirty two 4-KB Automotive AEC-Q100 Grade 1 ( 40C to +125C) sectors at top or bottom of address space with all remaining sectors of 64 KB, for compatibility with prior generation S25- Packages (all Pb-free) FL devices 16-lead SOIC (300 mil) Uniform sector option - always erase 256-KB blocks for soft- WSON 6 8 mm ware compatibility with higher density and future devices. BGA-24 6 8 mm Cycling Endurance 5 5 ball (FAB024) and 4 6 ball (FAC024) footprint 100,000 Program-Erase Cycles, minimum options Known Good Die (KGD) and Known Tested Die Logic Block Diagram CS SRAM SCK MirrorBit Array SI/IO0 SO/IO1 Y Decoders I/O Data Latch WP /IO2 Control Logic HOLD /IO3 Data Path RESET Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98283 Rev. *Q Revised April 30, 2019 X DecodersS25FL128S/S25FL256S Performance Summary Maximum Read Rates with the Same Core and I/O Voltage (V = V = 2.7V to 3.6V) IO CC Command Clock Rate (MHz) MBps Read 50 6.25 Fast Read 133 16.6 Dual Read 104 26 Quad Read 104 52 Maximum Read Rates with Lower I/O Voltage (V = 1.65V to 2.7V, V = 2.7V to 3.6V) IO CC Command Clock Rate (MHz) MBps Read 50 6.25 Fast Read 66 8.25 Dual Read 66 16.5 Quad Read 66 33 Maximum Read Rates DDR (V = V = 3V to 3.6V) IO CC Command Clock Rate (MHz) MBps Fast Read DDR 80 20 Dual Read DDR 80 40 Quad Read DDR 80 80 Typical Program and Erase Rates Operation KBps Page Programming (256-byte page buffer - Hybrid Sector Option) 1000 Page Programming (512-byte page buffer - Uniform Sector Option) 1500 4-KB Physical Sector Erase (Hybrid Sector Option) 30 64-KB Physical Sector Erase (Hybrid Sector Option) 500 256-KB Logical Sector Erase (Uniform Sector Option) 500 Current Consumption Operation Current (mA) Serial Read 50 MHz 16 (max) Serial Read 133 MHz 33 (max) Quad Read 104 MHz 61 (max) Quad DDR Read 80 MHz 90 (max) Program 100 (max) Erase 100 (max) Standby 0.07 (typ) Document Number: 001-98283 Rev. *Q Page 2 of 146