S25FL128S SUPPLEMENT S25FL256S 128 Mbit (16 Mbyte) and 256 Mbit (32 Mbyte), 3 V, MirrorBit Flash General Description This supplementary document provides information on a device designed for limited distribution. It describes how the features, operation, and ordering options of this device have been enhanced or changed from the standard device on which it is based. The information contained in this document modifies any information on the same topics established by the data sheets listed in the Affected Documents/Related Documents table and should be used in conjunction with those documents. This document may also contain information that was not previously covered by the S25FL128S and S25FL256S data sheets. It is intended for hardware system designers and software developers of applications, operating systems, or tools. Affected Documents/Related Documents Title Spansion Publication Number Cypress Document Number S25FL128S and S25FL256S Data Sheet S25FL128S 256S 00 001-98283 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00627 Rev. *D Revised June 09, 2017S25FL128S SUPPLEMENT S25FL256S 1. Device Description 1.1 Permanent Lock Description The Secure Model devices offer a unique Permanent Lock feature that allows the host system to permanently secure data in the memory array. Initiating this locking feature makes the selected block protection scheme permanent, thereby disabling both program and erase operations in the protected region of the array. 1.2 Advanced Sector Protection Description The secure model devices modify the Advanced Sector Protection (ASP) features: All Dynamic Protection Bits (DYB) are modified to be in the protected state following power-up All Persistent Protection Bits (PPB) are modified to be One Time Programmable (OTP). After a PPB bit is programmed, the related sector is permanently protected. PPB bits are not erasable. PPB bits may be programmed while the PPBLOCK Bit = 0. 2. Registers 2.1 Configuration Register 1 (CR1) Bit 4 called LOCK is added to CR1. When set to 1, the Block Protection configuration is permanent. Configuration Register (CR1) Default Bits Field Name Function Description State 7 LC1 0 Selects number of initial read latency cycles. See Latency Latency Code Code Tables. 6 LC0 0 Configures Start of Block Protection and selects readable 1 = BP starts at bottom (Low address) 5 TBPROT 0 boot sector in Read Password Mode 0 = BP starts at top (High address) Permanently locks BP2-0 and TBPROT bits in their state 1 = Locked 4 LOCK 0 when LOCK is set to 1 0 = Un-locked 1 = Volatile 3 BPNV Configures BP2-0 in Status Register 0 0 = Non-Volatile 1 = 4 kB physical sectors at top (High address) 0 = 4 kB physical sectors at bottom 2 TBPARM Configures Parameter Sectors location 0 (Low address) RFU in uniform sector devices. 1 = Quad 1 QUAD Puts the device into Quad I/O operation 0 0 = Dual or Serial Lock current state of BP2-0 bits in Status Register, 1 = Block Protection and OTP locked 0 FREEZE TBPROT, and TBPARM in Configuration Register, and OTP 0 0 = Block Protection and OTP un-locked regions Document Number: 002-00627 Rev. *D Page 2 of 8