S25FL128S/S25FL256S 128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte) 3.0V SPI Flash Memory Features CMOS 3.0 Volt Core with Versatile I/O Cycling Endurance 100,000 Program-Erase Cycles, minimum Serial Peripheral Interface (SPI) with Multi-I/O SPI Clock polarity and phase modes 0 and 3 Data Retention Double Data Rate (DDR) option 20 Year Data Retention, minimum Extended Addressing: 24- or 32-bit address options Security features Serial Command set and footprint compatible with One Time Program (OTP) array of 1024 bytes S25FL-A, S25FL-K, and S25FL-P SPI families Block Protection: Multi I/O Command set and footprint compatible with Status Register bits to control protection against S25FL-P SPI family program or erase of a contiguous range of sectors. READ Commands Hardware and software control options Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad Advanced Sector Protection (ASP) DDR Individual sector protection controlled by boot code or AutoBoot - power up or reset and execute a Normal or password Quad read command automatically at a preselected Cypress 65 nm MirrorBit Technology with Eclipse address Architecture Common Flash Interface (CFI) data for configuration Core Supply Voltage: 2.7V to 3.6V information. I/O Supply Voltage: 1.65V to 3.6V Programming (1.5 Mbytes/s) SO16 and FBGA packages 256 or 512 Byte Page Programming buffer options Temperature Range / Grade: Quad-Input Page Programming (QPP) for slow clock Industrial (-40C to +85C) systems Industrial Plus (-40C to +105C) Automatic ECC -internal hardware Error Correction Code Automotive AEC-Q100 Grade 3 (-40C to +85C) generation with single bit error correction Automotive AEC-Q100 Grade 2 (-40C to +105C) Erase (0.5 to 0.65 Mbytes/s) Automotive AEC-Q100 Grade 1 (-40C to +125C) Hybrid sector size option - physical set of thirty two 4-kbyte Packages (all Pb-free) sectors at top or bottom of address space with all 16-lead SOIC (300 mil) remaining sectors of 64 kbytes, for compatibility with prior WSON 6 x 8 mm generation S25FL devices BGA-24 6 x 8 mm Uniform sector option - always erase 256-kbyte blocks for software compatibility with higher density and future 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint devices. options Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98283 Rev. *N Revised June 14, 2017S25FL128S/S25FL256S Known Good Die and Known Tested Die Logic Block Diagram CS SRAM SCK MirrorBit Array SI/IO0 SO/IO1 Y Decoders I/O Data Latch WP /IO2 Control Logic HOLD /IO3 Data Path RESET Document Number: 001-98283 Rev. *N Page 2 of 146 X Decoders