S25FL256SAGMFBG00 Infineon

S25FL128S/S25FL256S 128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte) 3.0V SPI Flash Memory Features CMOS 3.0 Volt Core with Versatile I/O 100,000 Program-Erase Cycles, minimum Serial Peripheral Interface (SPI) with Multi-I/O Data Retention SPI Clock polarity and phase modes 0 and 3 20 Year Data Retention, minimum Double Data Rate (DDR) option Security features Extended Addressing: 24- or 32-bit address options One Time Program (OTP) array of 1024 bytes Serial Command set and footprint compatible with Block Protection: S25FL-A, S25FL-K, and S25FL-P SPI families Status Register bits to control protection against Multi I/O Command set and footprint compatible with program or erase of a contiguous range of sectors. S25FL-P SPI family Hardware and software control options READ Commands Advanced Sector Protection (ASP) Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad Individual sector protection controlled by boot code or DDR password AutoBoot - power up or reset and execute a Normal or Cypress 65 nm MirrorBit Technology with Eclipse Quad read command automatically at a preselected Architecture address Core Supply Voltage: 2.7V to 3.6V Common Flash Interface (CFI) data for configuration I/O Supply Voltage: 1.65V to 3.6V information. SO16 and FBGA packages Programming (1.5 Mbytes/s) Temperature Range / Grade: 256 or 512 Byte Page Programming buffer options Industrial (-40C to +85C) Quad-Input Page Programming (QPP) for slow clock Industrial Plus (-40C to +105C) systems Automotive AEC-Q100 Grade 3 (-40C to +85C) Automatic ECC -internal hardware Error Correction Code Automotive AEC-Q100 Grade 2 (-40C to +105C) generation with single bit error correction Automotive AEC-Q100 Grade 1 (-40C to +125C) Erase (0.5 to 0.65 Mbytes/s) Packages (all Pb-free) Hybrid sector size option - physical set of thirty two 4-kbyte 16-lead SOIC (300 mil) sectors at top or bottom of address space with all WSON 6 x 8 mm remaining sectors of 64 kbytes, for compatibility with prior BGA-24 6 x 8 mm generation S25FL devices 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint Uniform sector option - always erase 256-kbyte blocks for options software compatibility with higher density and future devices. Known Good Die and Known Tested Die Cycling Endurance Logic Block Diagram CS SRAM SCK MirrorBit Array SI/IO0 SO/IO1 Y Decoders I/O Data Latch WP /IO2 Control Logic HOLD /IO3 Data Path RESET Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98283 Rev. *O Revised March 21, 2018 X DecodersS25FL128S/S25FL256S Performance Summary Maximum Read Rates with the Same Core and I/O Voltage (V = V = 2.7V to 3.6V) IO CC Command Clock Rate (MHz) Mbytes/s Read 50 6.25 Fast Read 133 16.6 Dual Read 104 26 Quad Read 104 52 Maximum Read Rates with Lower I/O Voltage (V = 1.65V to 2.7V, V = 2.7V to 3.6V) IO CC Command Clock Rate (MHz) Mbytes/s Read 50 6.25 Fast Read 66 8.25 Dual Read 66 16.5 Quad Read 66 33 Maximum Read Rates DDR (V = V = 3V to 3.6V) IO CC Command Clock Rate (MHz) Mbytes/s Fast Read DDR 80 20 Dual Read DDR 80 40 Quad Read DDR 80 80 Typical Program and Erase Rates Operation kbytes/s Page Programming (256-byte page buffer - Hybrid Sector Option) 1000 Page Programming (512-byte page buffer - Uniform Sector Option) 1500 4-kbyte Physical Sector Erase (Hybrid Sector Option) 30 64-kbyte Physical Sector Erase (Hybrid Sector Option) 500 256-kbyte Logical Sector Erase (Uniform Sector Option) 500 Current Consumption Operation Current (mA) Serial Read 50 MHz 16 (max) Serial Read 133 MHz 33 (max) Quad Read 104 MHz 61 (max) Quad DDR Read 80 MHz 90 (max) Program 100 (max) Erase 100 (max) Standby 0.07 (typ) Document Number: 001-98283 Rev. *O Page 2 of 154