Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comS25FL512S Military 512 Mbit (64 Mbyte) 3.0V SPI Flash Memory Features CMOS 3.0 Volt Core with Versatile I/O Erase (0.5 to 0.65 Mbytes/s) Uniform 256-kbyte sectors Serial Peripheral Interface with Multi-I/O Cycling Endurance Density 100 Program-Erase Cycles 512 Mbits (64 Mbytes) Data Retention Serial Peripheral Interface (SPI) >20 Year Data Retention SPI Clock polarity and phase modes 0 and 3 Double Data Rate (DDR) option Security features Extended Addressing: 32-bit address One Time Program (OTP) array of 1024 bytes Serial Command set and footprint compatible with S25FL-A, Block Protection: S25FL-K, and S25FL-P SPI families Status Register bits to control protection against program or erase Multi I/O Command set and footprint compatible with of a contiguous range of sectors. S25FL-P SPI family Hardware and software control options Advanced Sector Protection (ASP) READ Commands Individual sector protection controlled by boot code or password Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR Cypress 65 nm MirrorBit Technology with Eclipse Architecture AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address Core Supply Voltage: 2.7V to 3.6V Common Flash Interface (CFI) data for configuration information. I/O Supply Voltage: 1.65V to 3.6V Programming (1.5 Mbytes/s) FBGA packages 512-byte Page Programming buffer Temperature Range: Quad-Input Page Programming (QPP) for slow clock systems Military (55C to +125C) Automatic ECC -internal hardware Error Correction Code Packages (Pb-free or Pb) generation with single bit error correction BGA-24 6 x 8 mm 5 x 5 ball (FAB024) footprint option Logic Block Diagram CS SRAM SCK MirrorBit Array SI/IO0 SO/IO1 Y Decoders I/O Data Latch WP /IO2 Control Logic HOLD /IO3 Data Path RESET Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-19087 Rev. *A Revised October 26, 2018 X Decoders