S25FL512S 512 Mbit (64 Mbyte), 3.0 V SPI Flash Memory Features CMOS 3.0 Volt Core with versatile I/O Data Retention Serial Peripheral Interface (SPI) with Multi-I/O 20 Year Data Retention, minimum Security features Density OTP array of 1024 bytes 512 Mbits (64 Mbytes) Block Protection: SPI Status Register bits to control protection against program SPI Clock polarity and phase modes 0 and 3 or erase of a contiguous range of sectors. Double Data Rate (DDR) option Hardware and software control options Extended Addressing: 32-bit address Advanced Sector Protection (ASP) Serial Command set and footprint compatible with Individual sector protection controlled by boot code or S25FL-A, S25FL-K, and S25FL-P SPI families password Multi I/O Command set and footprint compatible with Cypress 65 nm MirrorBit Technology with Eclipse S25FL-P SPI family Architecture READ Commands Core Supply Voltage: 2.7 V to 3.6 V Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR I/O Supply Voltage: 1.65 V to 3.6 V AutoBoot - power up or reset and execute a Normal or Quad SO16 and FBGA packages read command automatically at a preselected address Temperature Range: Common Flash Interface (CFI) data for configuration infor- mation. Industrial (40 C to +85 C) Programming (1.5 MB/s) Industrial Plus (40 C to +105 C) 512-byte Page Programming buffer Automotive, AEC-Q100 Grade 3 (40 C to +85 C) Quad-Input Page Programming (QPP) for slow clock sys- Automotive, AEC-Q100 Grade 2 (40 C to +105 C) tems Automotive, AEC-Q100 Grade 1 (40 C to +125 C) Automatic ECC -internal hardware Error Correction Code Packages (all Pb-free) generation with single bit error correction 16-lead SOIC (300 mil) Erase (0.5 to 0.65 MB/s) BGA-24 6 8 mm Uniform 256-kbyte sectors 5 5 ball (FAB024) and 4 6 ball (FAC024) footprint op- Cycling Endurance tions 100,000 Program-Erase Cycles, minimum Known Good Die and Known Tested Die Logic Block Diagram CS SRAM SCK MirrorBit Array SI/IO0 SO/IO1 Y Decoders I/O Data Latch WP /IO2 Control Logic HOLD /IO3 Data Path RESET Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98284 Rev. *P Revised June 22, 2018 X DecodersS25FL512S Performance Summary Maximum Read Rates with the Same Core and I/O Voltage (V = V = 2.7 V to 3.6 V) IO CC Command Clock Rate (MHz) Mbps Read 50 6.25 Fast Read 133 16.6 Dual Read 104 26 Quad Read 104 52 Maximum Read Rates with Lower I/O Voltage (V = 1.65 V to 2.7 V, V = 2.7 V to 3.6 V) IO CC Command Clock Rate (MHz) Mbps Read 50 6.25 Fast Read 66 8.25 Dual Read 66 16.5 Quad Read 66 33 Maximum Read Rates DDR (V = V = 3 V to 3.6 V) IO CC Command Clock Rate (MHz) Mbps Fast Read DDR 80 20 Dual Read DDR 80 40 Quad Read DDR 80 80 Typical Program and Erase Rates Operation kbytes/s Page Programming (512-byte page buffer - Uniform Sector Option) 1500 256-kbyte Logical Sector Erase (Uniform Sector Option) 500 Current Consumption Operation Clock Rate (MHz) Serial Read 50 MHz 16 (max) Serial Read 133 MHz 33 (max) Quad Read 104 MHz 61 (max) Program 100 (max) Erase 100 (max) Standby 0.07 (typ) Document Number: 001-98284 Rev. *P Page 2 of 146