Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comS25FL512S 512 Mbit (64 Mbyte), 3.0 V SPI Flash Memory Features CMOS 3.0 Volt Core with versatile I/O Data Retention Serial Peripheral Interface (SPI) with Multi-I/O 20-Year Data Retention, minimum Security features Density OTP array of 1024 bytes 512 Mbits (64 Mbytes) Block Protection: SPI Status Register bits to control protection against program SPI Clock polarity and phase modes 0 and 3 or erase of a contiguous range of sectors. Double Data Rate (DDR) option Hardware and software control options Extended Addressing: 32-bit address Advanced Sector Protection (ASP) Serial Command set and footprint compatible with Individual sector protection controlled by boot code or S25FL-A, S25FL-K, and S25FL-P SPI families password Multi I/O Command set and footprint compatible with the S25FL-P SPI family Cypress 65 nm MirrorBit Technology with Eclipse READ Commands Architecture Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR Core supply voltage: 2.7 V to 3.6 V AutoBoot - power up or reset and execute a Normal or Quad I/O supply voltage: 1.65 V to 3.6 V read command automatically at a preselected address SO16 and FBGA packages Common Flash Interface (CFI) data for configuration infor- Temperature range: mation. Programming (1.5 MBps) Industrial (40 C to +85 C) Industrial Plus (40 C to +105 C) 512-byte Page Programming buffer Automotive, AEC-Q100 Grade 3 (40 C to +85 C) Quad-Input Page Programming (QPP) for slow clock sys- tems Automotive, AEC-Q100 Grade 2 (40 C to +105 C) Automatic ECC -internal hardware Error Correction Code Automotive, AEC-Q100 Grade 1 (40 C to +125 C) generation with single bit error correction Packages (all Pb-free) Erase (0.5 to 0.65 MBps) 16-pin SOIC (300 mil) Uniform 256-kbyte sectors 24-BGA (6 8 mm) Cycling Endurance 5 5 ball (FAB024) and 4 6 ball (FAC024) footprint options 100,000 Program-Erase Cycles, minimum Known Good Die and Known Tested Die Logic Block Diagram CS SRAM SCK MirrorBit Array SI/IO0 SO/IO1 Y Decoders I/O Data Latch WP /IO2 Control Logic HOLD /IO3 Data Path RESET Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98284 Rev. *Q Revised January 23, 2019 X Decoders