Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comS25FS512S 512 Mb, 1.8 V Serial Peripheral Interface with Multi-I/O Flash Features Serial Peripheral Interface (SPI) with Multi-I/O Data Retention SPI Clock polarity and phase modes 0 and 3 20 Year Data Retention, minimum Double Data Rate (DDR) option Security Features Extended Addressing 24 or 32-bit address options One Time Program (OTP) array of 1024 bytes Serial Command subset and footprint compatible with Block Protection: S25FL-A, S25FL-K, S25FL-P, and S25FL-S SPI families Status Register bits to control protection against program Multi I/O Command subset and footprint compatible with or erase of a contiguous range of sectors. S25FL-P, and S25FL-S SPI families Hardware and software control options Read Advanced Sector Protection (ASP) Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad I/O Individual sector protection controlled by boot code or Modes: Burst Wrap, Continuous (XIP), QPI password Serial Flash Discoverable Parameters (SFDP) and Common Option for password control of read access Flash Interface (CFI), for configuration information. Technology Program Cypress 65-nm MirrorBit Technology with Eclipse 256 or 512 Bytes Page Programming buffer Architecture Program suspend and resume Supply Voltage Automatic Error Checking and Correction (ECC) internal hardware ECC with single bit error correction 1.7 V to 2.0 V Erase Temperature Range / Grade Hybrid sector option Industrial ( 40 C to +85 C) Physical set of eight 4-KB sectors and one Industrial Plus ( 40 C to +105 C) 224-KB sector at the top or bottom of address space with Automotive, AEC-Q100 Grade 3 (40 C to +85 C) all remaining sectors of 256-KB Automotive, AEC-Q100 Grade 2 (40 C to +105 C) Uniform sector option Automotive, AEC-Q100 Grade 1 (40 C to +125 C) Uniform 256-KB blocks Packages (all Pb-free) Erase suspend and resume 16-lead SOIC 300 mil (SO3016) Erase status evaluation WSON 6 8 mm (WNH008) Cycling Endurance BGA-24 6 8 mm 100,000 Program-Erase Cycles, minimum 5 5 ball (FAB024) footprint Known Good Die and Known Tested Die Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00488 Rev. *M Revised November 22, 2019