S25FS512S 512 Mbit, 1.8 V Serial Peripheral Interface with Multi-I/O Flash Features Serial Peripheral Interface (SPI) with Multi-I/O Data Retention SPI Clock polarity and phase modes 0 and 3 20 Year Data Retention, minimum Double Data Rate (DDR) option Security Features Extended Addressing 24 or 32-bit address options One Time Program (OTP) array of 1024 bytes Serial Command subset and footprint compatible with Block Protection: S25FL-A, S25FL-K, S25FL-P, and S25FL-S SPI families Status Register bits to control protection against program Multi I/O Command subset and footprint compatible with or erase of a contiguous range of sectors. S25FL-P, and S25FL-S SPI families Hardware and software control options Read Advanced Sector Protection (ASP) Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad I/O Individual sector protection controlled by boot code or Modes: Burst Wrap, Continuous (XIP), QPI password Serial Flash Discoverable Parameters (SFDP) and Common Option for password control of read access Flash Interface (CFI), for configuration information. Technology Program Cypress 65-nm MirrorBit Technology with Eclipse 256 or 512 Bytes Page Programming buffer Architecture Program suspend and resume Supply Voltage Automatic Error Checking and Correction (ECC) internal hardware ECC with single bit error correction 1.7 V to 2.0 V Erase Temperature Range / Grade Hybrid sector option Industrial ( 40 C to +85 C) Physical set of eight 4-kbytes sectors and one Industrial Plus ( 40 C to +105 C) 224-kbytes sector at the top or bottom of address space Automotive, AEC-Q100 Grade 3 (40 C to +85 C) with all remaining sectors of 256 kbytes Automotive, AEC-Q100 Grade 2 (40 C to +105 C) Uniform sector option Automotive, AEC-Q100 Grade 1 (40 C to +125 C) Uniform 256 kbyte blocks Packages (all Pb-free) Erase suspend and resume 16-lead SOIC 300 mil (SO3016) Erase status evaluation WSON 6 8 mm (WNH008) Cycling Endurance BGA-24 6 8 mm 100,000 Program-Erase Cycles, minimum 5 5 ball (FAB024) footprint Known Good Die and Known Tested Die Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00488 Rev. *I Revised April 06, 2018S25FS512S Logic Block Diagram CS SRAM SCK MirrorBit Array SI/IO0 I/O Y Decoders SO/IO1 Data Latch Control WP /IO2 Logic RESET /IO3 Data Path Performance Summary Maximum Read Rates Command Clock Rate (MHz) Mbytes/s Read 50 6.25 Fast Read 133 16.5 Dual Read 133 33 Quad Read 133 66 DDR Quad I/O Read 80 80 Typical Program and Erase Rates Operation kbytes/s Page Programming (256-bytes page buffer) 712 Page Programming (512-bytes page buffer) 1080 4-kbytes Physical Sector Erase (Hybrid Sector Option) 28 256-kbytes Sector Erase (Uniform Logical Sector Option) 250 Typical Current Consumption, 40C to +85C Operation Current (mA) Serial Read 50 MHz 10 Serial Read 133 MHz 20 Quad Read 133 MHz 60 Quad DDR Read 80 MHz 70 Program 60 Erase 60 Standby 0.07 Deep Power Down 0.006 Document Number: 002-00488 Rev. *I Page 2 of 136 X Decoders