S25HS256T, S25HS512T, S25HS01GT, S25HL256T, S25HL512T, S25HL01GT 256Mb/512Mb/1Gb SEMPER Flash Quad SPI, 1.8V/3.0V Features CYPRESS 45-nm MIRRORBIT technology that stores two data bits in each memory array cell Sector architecture options - Uniform: Address space consists of all 256KB sectors - Hybrid Configuration 1: Address space consists of thirty-two 4KB sectors grouped either on the top or the bottom while the remaining sectors are all 256KB - Hybrid Configuration 2: Address space consists of thirty-two 4KB sectors equally split between top and bottom while the remaining sectors are all 256KB Page programming buffer of 256 or 512 bytes OTP secure silicon array of 1024 bytes (32 32 bytes) Quad SPI - Supports 1S-1S-4S, 1S-4S-4S, 1S-4D-4D, 4S-4S-4S, 4S-4D-4D protocols - SDR option runs up to 83-Mbps (166MHz clock speed) - DDR option runs up to 102-Mbps (102MHz clock speed) Dual SPI - Supports 1S-2S-2S protocol - SDR option runs up to 41.5-Mbps (166MHz clock speed) SPI - Supports 1S-1S-1S protocol - SDR option runs up to 21-Mbps (166MHz clock speed) Functional safety features - Functional safety with the industrys first ISO26262 ASIL B compliant and ASIL D ready NOR Flash - Infineon Endurance Flex architecture provides high-endurance and long retention partitions - Data integrity CRC detects errors in memory array - SafeBoot reports device initialization failures, detects configuration corruption, and provides recovery op- tions - Built-in error correcting code (ECC) corrects single-bit error and detects double-bit error (SECDED) on memory array data - Sector erase status indicator for power loss during erase Protection features - Legacy block protection for memory array and device configuration - Advanced sector protection for individual memory array sector based protection AutoBoot enables immediate access to the memory array following power-on Hardware reset through CS Signaling method (JEDEC) / individual RESET pin / DQ3 RESET pin Serial flash discoverable parameters (SFDP) describing device functions and features Device identification, manufacturer identification, and unique identification Data Integrity - 256Mb devices Minimum 640,000 program-erase cycles for the main array - 512Mb devices Minimum 1,280,000 program-erase cycles for the main array -1Gb devices Minimum 2,560,000 program-erase cycles for the main array - All devices Minimum 300,000 program-erase cycles for the 4KB sectors Minimum 25 Years data retention Datasheet Please read the Important Notice and Warnings at the end of this document 002-12345 Rev. AA www.infineon.com page 1 of 141 2022-01-18 256Mb/512Mb/1Gb SEMPER Flash Quad SPI, 1.8V/3.0V Performance summary Supply voltage - 1.7V to 2.0V (HS-T) - 2.7V to 3.6V (HL-T) Grade / temperature range - Industrial ( 40C to +85C) - Industrial plus ( 40C to +105C) - Automotive AEC-Q100 grade 3 ( 40C to +85C) - Automotive AEC-Q100 grade 2 ( 40C to +105C) - Automotive AEC-Q100 grade 1 ( 40C to +125C) Packages - 256MB and 512MB 16-lead SOIC (300mil) - SO3016 24-ball BGA 6 8 mm 16-lead SOIC (300mil) 8-contact WSON 6 8 mm -1GB 16-lead SOIC (300mil) - SO3016 24-ball BGA 8 8 mm 16-lead SOIC (300mil) Performance summary Maximum read rates Transaction Initial access latency (Cycles) Clock rate (MHz) Mbps SPI Read 0 50 6.25 SPI Fast Read 9 166 20.75 Dual Read SDR 7 166 41.5 Quad Read SDR 10 166 83 Quad Read DDR 7 102 102 Typical Program and Erase rates Operation Kbps 256B page programming (4KB sector / 256KB sector) 595 / 533 512B page programming (4KB sector / 256KB sector) 753 / 898 256KB sector erase 331 4KB sector erase 95 Typical current consumption Operation Current (mA) SDR Read 50MHz 10 SDR Read 166MHz 53 DDR Read 102MHz 50 Program 50 Erase 50 Standby (HS-T) 0.011 Standby (HL-T) 0.014 Deep power down (HS-T) 0.0013 Deep power down (HL-T) 0.0022 Datasheet 2 of 141 002-12345 Rev. AA 2022-01-18