Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comS25HS02GT / S25HS04GT SUMMARY S25HL02GT / S25HL04GT 2-Gb (DDP), 4-Gb (QDP), HS-T (1.8-V), HL-T (3.0-V) Semper Flash with Quad SPI S25HS02GT / S25HS04GT / S25HL02GT / S25HL04GT 2-Gb (DDP), 4-Gb (QDP), HS-T (1.8-V), HL-T (3.0-V) Semper Flash with Quad SPI Device Overview Protection Features Architecture Legacy Block Protection for memory array and device con- Cypress 45-nm MirrorBit technology that stores two data figuration bits in each memory array cell Advanced Sector Protection for individual memory array sector based protection Multi-Chip Package (MCP) 02GT Dual Die Package (DDP) 2 1 Gb die Hardware Reset through CS Signaling method (JEDEC) / 04GT Quad Die Package (QDP) 4 1 Gb die individual RESET pin / DQ3 RESET pin Sector Architecture options Identification Uniform - Address space consists of all 256 KB Sectors Hybrid Serial Flash Discoverable Parameters (SFDP) describing Configuration 1: Address space consists of thirty-two 4 KB device functions and features sectors grouped either on the top or the bottom while the Device Identification, Manufacturer Identification, and Unique remaining sectors are all 256 KB Identification Configuration 2: Address space consists of thirty-two 4 KB sectors at the top and bottom while the remaining sectors are all 256 KB Data Integrity Page Programming buffer of 256 or 512 bytes 02GT DDP, 04GT QDP Devices Minimum 2,560,000 Program-Erase Cycles for the Main OTP Secure Silicon array of 1024 bytes (32 32 bytes) array All Devices Interface Minimum 300,000 Program-Erase Cycles for the 4 KB Quad SPI Sectors Supports 1S-1S-4S, 1S-4S-4S, 1S-4D-4D, 4S-4S-4S, Minimum 25 Years Data Retention 4S-4D-4D protocols SDR option runs up to 83 MBps (166 MHz clock speed) Supply Voltage DDR option runs up to 102 MBps (102 MHz clock speed) 1.7 V to 2.0 V (HS-T) Dual SPI 2.7 V to 3.6 V (HL-T) Supports 1S-2S-2S protocol SDR option runs up to 41.5 MBps (166 MHz clock speed) Grade / Temperature Range SPI Supports 1S-1S-1S protocol Industrial ( 40 C to +85 C) SDR option runs up to 21 MBps (166 MHz clock speed) Industrial Plus ( 40 C to +105 C) Automotive AEC-Q100 Grade 3 ( 40 C to +85 C) Highlights Automotive AEC-Q100 Grade 2 ( 40 C to +105 C) Safety Features Functional Safety with the Industrys first ISO26262 ASIL B Automotive AEC-Q100 Grade 1 ( 40 C to +125 C) compliant and ASIL D ready NOR flash EnduraFlex Architecture provides High-Endurance and Long Retention Partitions Packages Data Integrity CRC detects errors in memory array 02GT DDP, 04GT QDP Devices: SafeBoot reports device initialization failures, detects config- 24-ball BGA 8 8 mm uration corruption and provides recovery options Built-in Error Correcting Code (ECC) corrects Single-bit Error and detects Double-bit Error (SECDED) on memory array data Sector Erase Status indicator for power loss during erase Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-28767 Rev. ** Revised November 11, 2019