Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comS26HS256T/S26HS512T/S26HS01GT S26HL256T/S26HL512T/S26HL01GT 256-Mb (32-MB)/512-Mb (64-MB)/ 1-Gb (128-MB), HS-T (1.8-V)/HL-T (3.0-V), Semper Flash with HyperBus Interface S26HS512T / S26HS01GT / S26HL512T / S26HL01GT, 512-Mb (64-MB), 1-Gb (128-MB) HS-T (1.8-V), HL-T (3.0-V) Semper Flash with HyperBus Interface Protection Features Device Overview Advanced Sector Protection for individual memory array Architecture sector based protection Cypress 45-nm MirrorBit technology that stores two data bits AutoBoot enables immediate access to the memory array in each memory array cell following power-on Sector Architecture options Hardware Reset through CS Signaling method (JEDEC) AND individual RESET pin Uniform: Address space consists of all 256 KB Sectors Hybrid Identification Configuration 1: Address space consists of thirty-two 4 KB Serial Flash Discoverable Parameters (SFDP) describing sectors grouped either on the top or the bottom while the device functions and features remaining sectors are all 256 KB Configuration 2: Address space consists of thirty-two 4 KB Device Identification, Manufacturer Identification and Unique sectors equally split between top and bottom while the re- Identification maining sectors are all 256 KB Data Integrity Page Programming buffer of 256 or 512 bytes 256 Mb Devices OTP Secure Silicon Region (SSR) of 1024 bytes (32 32 bytes) Minimum 640,000 Program-Erase Cycles for the Main array Interface 512 Mb Devices Minimum 1,280,000 Program-Erase Cycles for the Main HyperBus Interface array JEDEC eXpanded SPI (JESD251) compliant 1 Gb Devices DDR option runs up to 400 MBps (200 MHz clock speed) Minimum 2,560,000 Program-Erase Cycles for the Main Supports Data Strobe (DS) to simplify the read data capture array in high-speed systems All Devices Legacy (x1) SPI (1S-1S-1S) Minimum 300,000 Program-Erase Cycles for the 4 KB JEDEC eXpanded SPI (JESD251) compliant Sectors SDR option runs up to 21 MBps (166 MHz clock speed) Minimum 25 Years Data Retention Semper Flash with HyperBus Interface devices support default boot in Legacy SPI (x1) or HyperBus Interface (x8) Supply Voltage 1.7-V to 2.0-V (HS-T) Highlights 2.7-V to 3.6-V (HL-T) Safety Features Functional Safety with the Industrys first ISO26262 ASIL B Grade/Temperature Range compliant and ASIL D ready NOR flash Industrial ( 40 C to +85 C) EnduraFlex Architecture provides High-Endurance and Long Retention Partitions Industrial Plus ( 40 C to +105 C) Interface CRC detects errors on communication interface be- tween host controller and Automotive AEC-Q100 Grade 3 ( 40 C to +85 C) Semper Flash device Automotive AEC-Q100 Grade 2 ( 40 C to +105 C) Data Integrity CRC detects errors in memory array SafeBoot reports device initialization failures, detects config- Automotive AEC-Q100 Grade 1 ( 40 C to +125 C) uration corruption, and provides recovery options Built-in Error Correcting Code (ECC) corrects Single-bit Error Packages and detects Double-bit Error (SECDED) on memory array 256 Mb and 512 Mb: data 24-ball BGA 6 8 mm Sector Erase Status indicator for power loss during erase 1 Gb: 24-ball BGA 8 8 mm Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-23879 Rev. *A Revised July 08, 2019