Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comS26KL512S/S26KS512S S26KL256S/S26KS256S S26KL128S/S26KS128S 512 Mb (64 MB)/256 Mb (32 MB)/ 128 Mb (16 MB), 1.8V/3.0V HyperFlash Family Features 3.0V I/O, 11 bus signals INT output to generate external interrupt Single ended clock Busy to Ready Transition ECC detection 1.8V I/O, 12 bus signals RSTO output to generate system level power-on reset Differential clock (CK, CK ) User configurable RSTO Low period Chip Select (CS ) 512-byte Program Buffer 8-bit data bus (DQ 7:0 ) Sector Erase Uniform 256-KB sectors Read-Write Data Strobe (RWDS) Optional Eight 4-KB Parameter Sectors (32 KB total) HyperFlash memories use RWDS only as a Read Data Strobe Advanced Sector Protection Volatile and Nonvolatile protection methods for each sector Up to 333 MBps sustained read throughput Separate 1024-byte one-time program array DDR two data transfers per clock Operating Temperature 166-MHz clock rate (333 MBps) at 1.8V V CC Industrial (40C to +85C) Industrial Plus (40C to +105C) 100-MHz clock rate (200 MBps) at 3.0V V CC Extended (40C to +125C) 96-ns initial random read access time Automotive, AEC-Q100 Grade 3 (40C to +85C) Initial random access read latency: 5 to 16 clock cycles Automotive, AEC-Q100 Grade 2 (40C to +105C) Automotive, AEC-Q100 Grade 1 (40C to +125C) Sequential burst transactions ISO/TS16949 and AEC Q100 Certified Configurable Burst Characteristics Endurance Wrapped burst lengths: 100,000 program/erase cycles 16 bytes (8 clocks) Retention 32 bytes (16 clocks) 20 year data retention 64 bytes (32 clocks) Erase and Program Current Linear burst Max Peak 100 mA Hybrid option: one wrapped burst followed by linear burst Packaging Options Wrapped or linear burst type selected in each transaction Configurable output drive strength 24-Ball FBGA Low Power Modes Additional Features Active Clock Stop During Read: 12 mA, no wake-up required ECC 1-bit correction, 2-bit detection Standby: 25 A (typical), no wake-up required CRC Deep Power-Down: 8 A (typical) 300 s wake-up required Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-99198 Rev. *M Revised June 12, 2019