Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comS28HS256T/S28HS512T/S28HS01GT S28HL256T/S28HL512T/S28HL01GT 256-Mb (32-MB)/512-Mb (64-MB)/ 1-Gb (128-MB), HS-T (1.8-V)/HL-T (3.0-V), Semper Flash with Octal Interface S28HS512T / S28HS01GT / S28HL512T / S28HL01GT, 512-Mb (64-MB), 1-Gb (128-MB), HS-T (1.8-V), HL-T (3.0-V), Semper Flash with Octal Interface AutoBoot enables immediate access to the memory array Device Overview following power-on Architecture Hardware Reset through CS Signaling method (JEDEC) OR individual RESET pin Cypress 45-nm MirrorBit technology that stores two data bits in each memory array cell Sector Architecture options Identification Uniform: Address space consists of all 256 KB Sectors Serial Flash Discoverable Parameters (SFDP) describing Hybrid: device functions and features Configuration 1 - Address space consists of thirty-two 4 KB Device Identification, Manufacturer Identification and Unique sectors grouped either on the top or the bottom while the Identification remaining sectors are all 256 KB Configuration 2 - Address space consists of thirty-two 4 KB sectors equally split between top and bottom while the re- Data Integrity maining sectors are all 256 KB 256 Mb Devices Page Programming buffer of 256 or 512 bytes Min. 640,000 Program-Erase Cycles for the Main array OTP Secure Silicon array of 1024 bytes (32 32 bytes) 512 Mb Devices Min. 1,280,000 Program-Erase Cycles for the Main array Interface 1 Gb Devices Octal Interface (8S-8S-8S, 8D-8D-8D) Min. 2,560,000 Program-Erase Cycles for the Main array JEDEC eXpanded SPI (JESD251) compliant All Devices SDR option runs up to 200 MBps (200 MHz clock speed) Min. 300,000 Program-Erase Cycles for the 4 KB Sectors DDR option runs up to 400 MBps (200 MHz clock speed) Minimum 25 Years Data Retention Supports Data Strobe (DS) to simplify the read data capture in high-speed systems Supply Voltage Serial Peripheral Interface (1S-1S-1S) JEDEC eXpanded SPI (JESD251) compliant 1.7-V to 2.0-V (HS-T) SDR option runs up to 21 MBps (166 MHz clock speed) 2.7-V to 3.6-V (HL-T) Highlights Grade/Temperature Range Safety Features Industrial ( 40 C to +85 C) Functional Safety with the Industrys first ISO26262 ASIL B compliant and ASIL D ready NOR flash Industrial Plus ( 40 C to +105 C) EnduraFlex Architecture provides High-Endurance and Automotive AEC-Q100 Grade 3 ( 40 C to +85 C) Long Retention Partitions Interface CRC detects errors on communication interface be- Automotive AEC-Q100 Grade 2 ( 40 C to +105 C) tween host controller and Semper Flash device Automotive AEC-Q100 Grade 1 ( 40 C to +125 C) Data Integrity CRC detects errors in memory array SafeBoot reports device initialization failures, detects config- Packages uration corruption and provides recovery options Built-in Error Correcting Code (ECC) corrects Single-bit Error 256 Mb and 512 Mb: and detects Double-bit Error (SECDED) on memory array 24-ball BGA 6 8 mm data Sector Erase Status indicator for power loss during erase 1 Gb: 24-ball BGA 8 8 mm Protection Features Legacy Block Protection for memory array and device con- figuration Advanced Sector Protection for individual memory array sector based protection Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-23881 Rev. *A Revised July 08, 2019