S29AL016J 16-Mbit (2M 8-Bit/1M 16-Bit), 3 V, Boot Sector Flash Distinctive Characteristics Architectural Advantages Performance Characteristics Single Power Supply Operation High Performance Full voltage range: 2.7 to 3.6 volt read and write operations Access times as fast as 55 ns for battery-powered applications Automotive, AEC-Q100 Grade 3 (40C to +85C) Manufactured on 110 nm Process Technology Automotive, AEC-Q100 Grade 1 (40C to +125C) Fully compatible with 200 nm S29AL016D Industrial temperature range (40C to +85C) Secured Silicon Sector region Extended temperature range (40C to +125C) Ultra Low Power Consumption (typical values at 5 MHz) 128-word/256-byte sector for permanent, secure identifica- tion through an 8-word/16-byte random Electronic Serial 0.2 A Automatic Sleep mode current Number accessible through a command sequence 0.2 A standby mode current May be programmed and locked at the factory or by the cus- 7 mA read current tomer 20 mA program/erase current Flexible Sector Architecture Cycling Endurance: 1,000,000 cycles per sector typical One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Data Retention: 20 years typical Kbyte sectors (byte mode) One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32 Package Options Kword sectors (word mode) Sector Group Protection Features 48-ball Fine-pitch BGA A hardware method of locking a sector to prevent any program 64-ball Fortified BGA or erase operations within that sector 48-pin TSOP Sectors can be locked in-system or via programming equip- ment Software Features Temporary Sector Unprotect feature allows code changes in previously locked sectors CFI (Common Flash Interface) Compliant Unlock Bypass Program Command Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Reduces overall programming time when issuing multiple program command sequences Erase Suspend/Erase Resume Top or Bottom Boot Block Configurations Available Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the Compatibility with JEDEC standards erase operation Pinout and software compatible with single-power supply Data Polling and Toggle Bits Flash Provides a software method of detecting program or erase Superior inadvertent write protection operation completion Hardware Features Ready/Busy Pin (RY/BY ) Provides a hardware method of detecting program or erase cycle completion Hardware Reset Pin (RESET ) Hardware method to reset the device to reading array data WP input pin For boot sector devices: at V , protects first or last 16 Kbyte IL sector depending on boot configuration (top boot or bottom boot) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00777 Rev. *Q Revised June 21, 2018S29AL016J General Description The S29AL016J is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball Fine-pitch BGA (0.8 mm pitch), 64-ball Fortified BGA (1.0 mm pitch) and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15DQ0 the byte-wide (x8) data appears on DQ7DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt V supply. A 12.0 V V or 5.0 V are not required for write or erase operations. The device can also CC PP CC be programmed in standard EPROM programmers. The device offers access time of 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE ), write enable (WE ) and output enable (OE ) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The S29AL016J is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithman internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY pin, or by reading the DQ7 (Data Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V detector that automatically inhibits write operations during power CC transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Cypress combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Document Number: 002-00777 Rev. *Q Page 2 of 57