S29AS016J 16 Mbit (2 M x 8-Bit/1 M x 16-Bit), 1.8 V Boot Sector Flash Distinctive Characteristics Word programming time as fast as 6 s (typical) Architectural Advantages Ultra Low Power Consumption (typical values at 5 MHz) Single Power Supply Operation 15 A Automatic Sleep mode current Full voltage range: 1.65 to 1.95 volt read and write operations for battery-powered applications 8 A standby mode current 8 mA read current Manufactured on 110 nm Process Technology 20 mA program/erase current Backward compatible with 0.32 m Am29SL160C device Cycling Endurance: 1,000,000 cycles per sector typical Secured Silicon Sector region 128-word/256-byte sector for permanent, secure Data Retention: 20 years typical identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence Package Options May be programmed and locked at the factory or by the 48-ball Fine-Pitch BGA, 8.15 mm x 6.15 mm customer 48-ball Fine-Pitch BGA, 6.0 mm x 4.0 mm Flexible Sector Architecture 48-pin TSOP Eight 8 Kbyte and thirty-one 64 Kbyte sectors (byte mode) Eight 4 Kword, and thirty-one 32 Kword sectors (word Software Features mode) CFI (Common Flash Interface) Compliant Sector Group Protection Features Provides device-specific information to the system, A hardware method of locking a sector to prevent any allowing host software to easily reconfigure for different program or erase operations within that sector Flash devices Sectors can be locked in-system or via programming Erase Suspend/Erase Resume equipment Suspends an erase operation to read data from, or Temporary Sector Group Unprotect feature allows code program data to, a sector that is not being erased, then changes in previously locked sectors resumes the erase operation Unlock Bypass Program Command Data Polling and Toggle Bits Reduces overall programming time when issuing multiple Provides a software method of detecting program or erase program command sequences operation completion Top or Bottom Boot Block Configurations Available Hardware Features Compatibility with JEDEC standards Ready/Busy Pin (RY/BY ) Pinout and software compatible with single-power supply Flash Provides a hardware method of detecting program or erase cycle completion Superior inadvertent write protection Hardware Reset Pin (RESET ) Performance Characteristics Hardware method to reset the device to reading array data High Performance WP input pin Access times as fast as 70 ns Write protect (WP ) function allows protection of two Industrial temperature range (-40C to +85C) outermost boot sectors (boot sector models only), Automotive In-Cabin temperature range (-40C to +105C) regardless of sector group protect status Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-01122 Rev.*L Revised May 31, 2017S29AS016J General Description The S29AS016J is a 16 Mbit, 1.8 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words with a x8/x16 bus and either top or bottom boot sector architecture. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word- wide data (x16) appears on DQ15DQ0 the byte-wide (x8) data appears on DQ7DQ0. This device is designed to be programmed and erased in-system with the standard system 1.8 volt V supply. A 12.0V V or 5.0 V are not required for CC PP CC program or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access time of 70 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE ), write enable (WE ) and output enable (OE ) controls. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The S29AS016J is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY pin, or by reading the DQ7 (Data Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V detector that automatically inhibits write operations during power CC transitions. The hardware sector group protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Cypress Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Document Number: 002-01122 Rev.*L Page 2 of 105