S29GL064S 64 Mbit (8 Mbyte) 3.0 V Flash Memory Distinctive Characteristics CMOS 3.0 Volt Core with Versatile I/O Low Power Consumption 25 mA typical initial read current 5 MHz Architectural Advantages 7.5 mA typical page read current 33 MHz 50 mA typical erase / program current Single Power Supply Operation 40 A typical standby mode current Manufactured on 65 nm MirrorBit Process Technology Package Options Secure Silicon Region 48-pin TSOP 128-word / 256-byte sector for permanent, secure identification 56-pin TSOP through an 8-word / 16-byte random Electronic Serial Number, accessible through a command sequence 64-ball Fortified BGA (LAA064 13 mm x 11 mm x 1.4 mm) (LAE064 9 mm x 9 mm x 1.4 mm) Programmed and locked at the factory or by the customer 48-ball fine-pitch BGA (VBK048 8.15 mm x 6.15 mm x 1.0 mm) Flexible Sector Architecture Temperature Range 64 Mb (uniform sector models): One hundred twenty-eight 32- kword (64-kB) sectors Industrial (-40C to +85C) 64 Mb (boot sector models): One hundred twenty-seven 32-kword Industrial Plus (-40C to +105C) (64-kB) sectors + eight 4kword (8kB) boot sectors Automotive, AEC-Q100 Grade 3 (-40C to +85C) Automatic Error Checking and Correction (ECC) - internal hardware Automotive, AEC-Q100 Grade 2(-40C to +105C) ECC with single bit error correction Enhanced VersatileI/O Control Software and Hardware Features All input levels (address, control, and DQ input levels) and outputs Software Features are determined by voltage on V input. V range is 1.65 to V IO IO CC Advanced Sector Protection: offers Persistent Sector Protection Compatibility with JEDEC Standards and Password Sector Protection Provides pinout and software compatibility for single-power supply Program Suspend and Resume: read other sectors before flash, and superior inadvertent write protection programming operation is completed Erase Suspend and Resume: read / program other sectors before 100,000 Erase Cycles per Sector Minimum an erase operation is completed 20-year Data Retention Typical Data polling and toggle bits provide status CFI (Common Flash Interface) compliant: allows host system to Performance Characteristics identify and accommodate multiple flash devices High Performance Unlock Bypass Program command reduces overall multiple-word 70 ns access time programming time 8-word / 16-byte page read buffer Hardware Features 15 ns page read time WP /ACC input supports manufacturing programming operations 128-word / 256-byte write buffer which reduces overall (when high voltage is applied). Protects first or last sector programming time for multiple-word updates regardless of sector protection settings on uniform sector models Hardware reset input (RESET ) resets device Ready/Busy output (RY/BY ) detects program or erase cycle completion Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98286 Rev. *F Revised June 08, 2017S29GL064S General Description The S29GL-S mid density family of devices are 3.0-volt single-power flash memory manufactured using 65 nm MirrorBit technology. The S29GL064S is a 64-Mb device organized as 4,194,304 words or 8,388,608 bytes. Depending on the model number, the devices have 16-bit wide data bus only, or a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE input. The devices can be programmed either in the host system or in standard EPROM programmers. Access times as fast as 70 ns are available. Note that each access time has a specific operating voltage range (V ) as specified in CC the Product Selector Guide and Ordering Information. Package offerings include 48-pin TSOP, 56-pin TSOP, 48-ball fine-pitch BGA, and 64-ball Fortified BGA, depending on model number. Each device has separate chip enable (CE ), write enable (WE ) and output enable (OE ) controls. Each device requires only a single 3.0-volt power supply for both read and write functions. In addition to a V input, a high- CC voltage accelerated program (ACC) feature is supported through increased voltage on the WP /ACC or ACC input. This feature is intended to facilitate system production. The device is entirely command set compatible with the JEDEC single-power-supply flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. The Advanced Sector Protection features several levels of sector protection, which can disable both the program and erase operations in certain sectors. Persistent Sector Protection is a method that replaces the previous 12-volt controlled protection method. Password Sector Protection is a highly sophisticated protection method that requires a password before changes to certain sectors are permitted. Device programming and erasure are initiated through command sequences. Once a program or erase operation begins, the host system need only poll the DQ7 (Data Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy (RY/BY ) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. Hardware data protection measures include a low V detector that automatically inhibits write operations during power CC transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend / Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend / Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE and RESET , or when addresses are stable for a specified period of time. The Write Protect (WP ) feature protects the first or last sector by asserting a logic low on the WP /ACC pin or WP pin, depending on model number. The protected sector is still protected even during accelerated programming. The Secure Silicon Region provides a 128-word / 256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. Cypress MirrorBit flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection. Document Number: 001-98286 Rev. *F Page 2 of 109