S29GL512N S29GL256N S29GL128N 512, 256, 128 Mbit, 3 V, Page Flash Featuring 110 nm MirrorBit This product family has been retired and is not recommended for designs. For new and current designs, S29GL128S, S29GL256S, and S29GL512T supersede the S29GL128N, S29GL256N, and S29GL512N respectively. These are the factory-recommended migration paths. Please refer to the S29GL-S and S29GL-T Family data sheets for specifications and ordering information. Distinctive Characteristics Package Options Architectural Advantages 56-pin TSOP Single Power Supply Operation 64-ball Fortified BGA 3 volt read, erase, and program operations Enhanced VersatileI/O Control Software & Hardware Features All input levels (address, control, and DQ input levels) and outputs Software Features are determined by voltage on V input. V range is 1.65 to V IO IO CC Program Suspend and Resume: read other sectors before Manufactured on 110 nm MirrorBit Process Technology programming operation is completed Secured Silicon Sector Region Erase Suspend and Resume: read/program other sectors before 128-word/256-byte sector for permanent, secure identification an erase operation is completed through an 8-word/16-byte random Electronic Serial Number, Data polling and toggle bits provide status accessible through a command sequence Unlock Bypass Program command reduces overall multiple-word May be programmed and locked at the factory or by the customer programming time Flexible Sector Architecture CFI (Common Flash Interface) compliant: allows host system to S29GL512N: Five hundred twelve 64 Kword (128 Kbyte) sectors identify and accommodate multiple flash devices S29GL256N: Two hundred fifty-six 64 Kword (128 Kbyte) sectors Hardware Features S29GL128N: One hundred twenty-eight 64 Kword (128 Kbyte) Advanced Sector Protection sectors WP /ACC input accelerates programming time (when high Compatibility with JEDEC Standards voltage is applied) for greater throughput during system Provides pinout and software compatibility for single-power supply production. Protects first or last sector regardless of sector flash, and superior inadvertent write protection protection settings 100,000 Erase Cycles per sector typical Hardware reset input (RESET ) resets device 20-year Data Retention typical Ready/Busy output (RY/BY ) detects program or erase cycle completion Performance Characteristics Product Availability Table High Performance 90 ns access time (S29GL128N, S29GL256N) Density Init. Access V Availability CC 100 ns (S29GL512N) 110 ns Full Now 8-word/16-byte page read buffer 512 Mb 100 ns Full Now 25 ns page read times 110 ns Full Now 16-word/32-byte write buffer reduces overall programming time for multiple-word updates 256 Mb 100 ns Full Now Low Power Consumption (typical values at 3.0 V, 5 MHz) 90 ns Regulated Now 25 mA typical active read current 110 ns Full Now 50 mA typical erase/program current 1 A typical standby mode current 128 Mb 100 ns Full Now 90 ns Regulated Now Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-01522 Rev. *B Revised January 08, 2016 Not Recommended for New DesignS29GL512N S29GL256N S29GL128N General Description The S29GL512/256/128N family of devices are 3.0V single power flash memory manufactured using 110 nm MirrorBit technology. The S29GL512N is a 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256 Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128N is a 128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The devices have a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE input. The device can be programmed either in the host system or in standard EPROM programmers. Access times as fast as 90 ns (S29GL128N, S29GL256N), 100 ns (S29GL512N) are available. Note that each access time has a specific operating voltage range (V ) and an I/O voltage range (V ), as specified in the Product Selector Guide on page 4 and the CC IO Ordering Information on page 9. The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable (CE ), write enable (WE ) and output enable (OE ) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V input, a high- CC voltage accelerated program (WP /ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The devices are entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 (Data Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy (RY/BY ) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. The Enhanced VersatileI/O (V ) control allows the host system to set the voltage levels that the device generates and tolerates IO on all input levels (address, chip control, and DQ input levels) to the same voltage level that is asserted on the V pin. This allows IO the device to operate in a 1.8 V or 3 V system environment as required. Hardware data protection measures include a low V detector that automatically inhibits write operations during power CC transitions. Persistent Sector Protection provides in-system, command-enabled protection of any combination of sectors using a single power supply at V . Password Sector Protection prevents unauthorized write and erase operations in any combination of CC sectors through a user-defined 64-bit password. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE and RESET , or when addresses have been stable for a specified period of time. The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. The Write Protect (WP /ACC) feature protects the first or last sector by asserting a logic low on the WP pin. MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection. Document Number: 002-01522 Rev. *B Page 2 of 92 Not Recommended for New Design