S29PL-J 128-/128-/64-/32-Mbit (8/8/4/2M 16-Bit), 3 V, Flash with Enhanced VersatileIO Distinctive Characteristics Output voltage generated and input voltages tolerated on Architectural Advantages all control inputs and I/Os is determined by the voltage on 128-/128-/64-/32-Mbit Page Mode devices the V pin Page size of 8 words: Fast page read access from random IO V options at 1.8 V and 3 V I/O for PL127J and PL129J locations within the page IO devices Single power supply operation 3V V for PL064J and PL032J devices Full Voltage range: 2.7 to 3.6 V read, erase, and program IO Secured Silicon Sector region operations for battery-powered applications Up to 128 words accessible through a command sequence Dual Chip Enable inputs (only in PL129J) Up to 64 factory-locked words Two CE inputs control selection of each half of the Up to 64 customer-lockable words memory space Both top and bottom boot blocks in one device Simultaneous Read/Write Operation Manufactured on 110-nm process technology Data can be continuously read from one bank while Data Retention: 20 years typical executing erase/program functions in another bank Zero latency switching from write to read operations Cycling Endurance: 1 million cycles per sector typical FlexBank Architecture (PL127J/PL064J/PL032J) Performance Characteristics 4 separate banks, with up to two simultaneous operations High Performance per device Page access times as fast as 20 ns Bank A: Random access times as fast as 55 ns PL127J -16 Mbit (4 Kw 8 and 32 Kw 31) Power consumption (typical values at 10 MHz) PL064J - 8 Mbit (4 Kw 8 and 32 Kw 15) 45 mA active read current PL032J - 4 Mbit (4 Kw 8 and 32 Kw 7) 17 mA program/erase current Bank B: 0.2 A typical standby mode current PL127J - 48 Mbit (32 Kw 96) PL064J - 24 Mbit (32 Kw 48) Software Features PL032J - 12 Mbit (32 Kw 24) Software command-set compatible with JEDEC 42.4 Bank C: standard PL127J - 48 Mbit (32 Kw 96) Backward compatible with Am29F, Am29LV, Am29DL, and PL064J - 24 Mbit (32 Kw 48) AM29PDL families and MBM29QM/RM, MBM29LV, PL032J - 12 Mbit (32 Kw 24) MBM29DL, MBM29PDL families Bank D: CFI (Common Flash Interface) compliant PL127J -16 Mbit (4 Kw 8 and 32 Kw 31) Provides device-specific information to the system, PL064J - 8 Mbit (4 Kw 8 and 32 Kw 15) allowing host software to easily reconfigure for different PL032J - 4 Mbit (4 Kw 8 and 32 Kw 7) Flash devices FlexBank Architecture (PL129J) Erase Suspend / Erase Resume 4 separate banks, with up to two simultaneous operations Suspends an erase operation to allow read or program per device operations in other sectors of same bank CE 1 controlled banks: Bank 1A: PL129J - 16-Mbit (4Kw 8 and 32Kw 31) Program Suspend / Program Resume Bank 1B: PL129J - 48-Mbit (32Kw 96) Suspends a program operation to allow read operation CE 2 controlled banks: from sectors other than the one being programmed Bank 2A: PL129J - 48-Mbit (32 Kw 96) Unlock Bypass Program command Bank 2B: PL129J - 16-Mbit (4 Kw 8 and 32 Kw 31) Reduces overall programming time when issuing multiple Enhanced VersatileI/O (V ) Control program command sequences IO Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00615 Rev. *D Revised May 31, 2017S29PL-J Hardware Features Password Sector Protection A sophisticated sector protection method to lock Ready/Busy pin (RY/BY ) combinations of individual sectors and sector groups to Provides a hardware method of detecting program or prevent program or erase operations within that sector erase cycle completion using a user-defined 64-bit password Hardware reset pin (RESET ) Package options Hardware method to reset the device to reading array data Standard discrete pinouts WP / ACC (Write Protect/Acceleration) input 11 8 mm, 80-ball Fine-pitch BGA (PL127J) (VBG080) At V , hardware level protection for the first and last two IL 8.15 6.15 mm, 48-ball Fine pitch BGA (PL064J/PL032J) 4K word sectors. (VBK048) At V , allows removal of sector protection IH MCP-compatible pinout At V , provides accelerated programming in a factory HH 8 11.6 mm, 64-ball Fine-pitch BGA (PL127J) setting 7 9 mm, 56-ball Fine-pitch BGA (PL064J and PL032J) Persistent Sector Protection Compatible with MCP pinout, allowing easy integration of A command sector protection method to lock RAM into existing designs combinations of individual sectors and sector groups to 20 14 mm, 56-pin TSOP (PL127J) (TS056) prevent program or erase operations within that sector Sectors can be locked and unlocked in-system at V CC level Document Number: 002-00615 Rev. *D Page 2 of 102