S72XS-R MCP 256 Mb (16M x 16 bit), 1.8V MirrorBit Flash and DDR DRAM Features General Description Power supply voltage This datasheet contains information on the S72XS-R Multi-Chip Product (MCP) stacked products. Refer to the S29VS256R, 1.7V to 1.95V S29VS128R, S29XS256R, S29XS128R datasheet (002-00833) Burst speed for full electrical specifications of the Flash memory component. Flash = 83 MHz, 104 MHz or 108 MHz The S72XS series is a product line of stacked products (MCPs), and DDR DRAM = 166 MHz consists of: Packages S29XS family Address-High, Address-Low, Data Multiplexed 8.0 8.0 mm, 133-ball MCP Flash memory die Temperature range DDR DRAM Wireless: 25 C to +85 C Table 1 and Table 2 lists the products covered in this datasheet. Industrial: 40 C to +85 C Table 1. Memory Density Flash Density DRAM Density 256 Mb S72XS256RE0 Table 2. DDR DRAM Specification Reference Density Reference Name Document Identification Number 256 Mb 256 Mb (16M 16-bit) DDR DRAM SDM256D166D1R/D3R Block Diagram F-RST RST A DQ15-A DQ0 ADQ15-ADQ0 A max-A 16 (No Connect) VPP CLK F-VPP F-CLK NOR RDY F-RDY F-CE CE FLASH F-OE OE XS-R F-W E WE F-AVD AVD (AADM) VCC F-VCC V CCQ F-VCCQ VSS VSS V SSQ D-RAS RA S CK D-CLK CA S CK D-CAS D-CLK D-BA0 BA 0 LDQS D-LDQS BA 1 DDR UDQS D-BA1 D-UDQS D-CKE CKE LDM D-LDQM DRAM D-W E WE UDM D-UDQM MEMORY D-CE CS D-Am ax - D-A0 A max-A 0 DQ15-DQ0 D-DQ15 - D-DQ0 D-VCC VDD VSS VSS D-VCCQ V DDQ V SSQ Notes 1. Amax indicates highest address bit for memory component: Amax = A12 for 256 Mb DDR DRAM. 2. For Flash, A15 - A0 is tied to DQ15 - DQ0. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00772 Rev. *J Revised March 18, 2016 S72XS-R MCP Pin Diagram Figure 1. 133-Ball Fine-Pitch Ball Grid Array MCP 12934756810 11 12 13 14 Legend A Index Location DNU DNU VSS D-VCCQ D-DQ9 D-DQ8 VSS D-VCC D-VCC D-DQ5 D-DQ3 VSS DNU DNU B DNU VSS D-DQ13 D-UDQS D-DQ10 VSS D-VCCQD-VCCQD-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ DNU Do Not Use C D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM VSS D-VCC VSS D-DQ7 D-LDQS D-DQ2 D-DQ0 VSS No Connect D RFU NC NC INDEX F-OE ADQ8 D-VCC DRAM Only E RFU RFU RFU ADQ9 ADQ1 ADQ0 Code Flash Only F RFU RFU RFU VSS ADQ3 ADQ2 Reserved for Future Use G F-CE RFU F-WE F-VCCQ ADQ11 ADQ10 VSS H F-VPP F-VCC F-CLK ADQ13 ADQ12 ADQ4 J RFU VSS NC VSS VSS ADQ5 K RFU F-AVD NC NC ADQ7 ADQ6 L RFU F-RST D-CE F-VCCQ ADQ15 ADQ14 M NC RFU D-A3 D-A6 D-A9 D-CKE VSS D-WE D-A10 D-A1 RFU RFU F-RDY VSS N DNU VSS D-VCC D-A5 D-A8 D-CAS D-CLK D-BA1 D-A11 D-A2 D-A12 RFU F-VCC DNU P DNU DNU NC D-A4 D-A7 D-RAS D-CLK D-VCC D-BA0 D-A0 D-VCC VSS DNU DNU Table 3. DRAM Address Maximum MCP Device ID DDR DRAM Density D-Amax S72XS256RE0 256 Mb D-A12 Document Number: 002-00772 Rev. *J Page 2 of 7