S79FL01GS 1-Gbit (128 MB) Dual-Quad MirrorBit Flash NVM CMOS 3.0 V Core SPI with Multi-I/O Features Density Cypress 65 nm MirrorBit Technology with Eclipse Architecture 1 Gbit (128 Mbytes) Core Supply Voltage: 2.7 V to 3.6 V Serial Peripheral Interface (SPI) SPI clock polarity and phase modes 0 and 3 Temperature Range: Double data rate (DDR) option Industrial (40 C to +85 C) Extended addressing: 32-bit address Industrial Plus (40 C to +105 C) Automotive, AEC-Q100 Grade 3 (40 C to +85 C) READ Commands Automotive, AEC-Q100 Grade 2 (40 C to +105 C) Dual-Quad SPI Quad Read: 104 MHz clock rate (104 MB/s) Packages (all Pb-free) Dual-Quad SPI Quad DDR Read: 80 MHz clock rate BGA-24 6 8 mm (160 MB/s) 5 5 ball (ZSA024) footprint Normal, Fast, Quad, Quad DDR Software Features AutoBoot - power up or reset and execute a Normal or Program suspend and resume Quad read command automatically at a preselected Erase suspend and resume address Status register provides status of embedded erase or Common flash interface (CFI) data for configuration programming operation information. CFI-compliant allows the host system to identify the Programming (3 Mbytes/s) flash device and determine its capabilities 1024-byte page programming buffer JEDEC JESD216 Serial Flash Discoverable Parameter Quad-input page programming (QPP) for slow clock (SFDP) support systems User-configurable configuration register Automatic error checking and correction (ECC) internal Hardware Features hardware ECC with single bit error correction Hardware reset input (RESET ) resets device to Erase (1 Mbyte/s) standby state Uniform 512-kbyte sectors Extended addressing: 24- or 32-bit address options Cycling Endurance 100,000 program-erase cycles, minimum Data Retention 20 year data retention, minimum Security Features Separate one time program (OTP) array of 2048 bytes Block protection: Status register bits to control protection against program or erase of a contiguous range of sectors Hardware and software control options Advanced sector protection (ASP) Individual sector protection controlled by boot code or password Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00466 Rev. *G Revised March 20, 2018S79FL01GS Performance Summary Maximum Read Rates SDR Dual-Quad SPI (V = 2.7 V to 3.6 V) CC Command Clock Rate (MHz) Mbytes/s Read 50 12.5 Fast Read 133 33 Quad Read 104 104 Maximum Read Rates DDR Dual-Quad SPI (V = 3 V to 3.6 V) CC Command Clock Rate (MHz) Mbytes/s DDR Quad Read 80 160 Typical Program and Erase Rates Dual-Quad SPI Operation kbytes/s Page Programming (1024-byte page buffer) 3000 512-kbyte Logical Sector Erase 1000 Typical Current Consumption, Dual-Quad SPI Operation Current (mA) Serial Read 50 MHz 32 (max) Serial Fast Read 133 MHz 66 (max) Quad Read 104 MHz 122 (max) Program 200 (max) Erase 200 (max) Standby 0.14 (typ) Document Number: 002-00466 Rev. *G Page 2 of 119