Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comS79FL256S/S79FL512S 256 Mb (32 MB)/512 Mb (64 MB), 3 V Dual-Quad SPI Flash S79FL256S/S79FL512S, 256 Mb (32 MB)/512 Mb (64 MB), 3 V, Dual-Quad SPI Flash Features Density Security Features 256 Mb (32 MB) Separate One Time Program (OTP) array of 2048 bytes 512 Mb (64 MB) Block Protection: Status Register bits to control protection against program SPI or erase of a contiguous range of sectors. SPI Clock polarity and phase modes 0 and 3 Hardware and software control options DDR option Advanced Sector Protection (ASP) Extended Addressing: 24- or 32-bit address options Individual sector protection controlled by boot code or READ Commands password Dual-Quad SPI Quad Read: 104 MHz clock rate (104 MB/s) Cypress 65 nm MirrorBit Technology with Eclipse Archi- Dual-Quad SPI Quad DDR Read: 80 MHz clock rate (160 tecture MBps) Normal, Fast, Quad, Quad DDR Core Supply Voltage: 2.7V to 3.6V AutoBoot - power up or reset and execute a Normal or Quad Temperature Range: read command automatically at a preselected address Industrial (-40C to +85C) Common Flash Interface (CFI) data for configuration infor- mation. Industrial Plus (-40C to +105C) Automotive, AEC-Q100 Grade 3 (-40C to +85C) Programming (3 MBps) Automotive, AEC-Q100 Grade 2 (-40C to +105C) 512-byte or 1024-byte Page Programming buffer options Packages (all Pb-free) Quad-Input Page Programming (QPP) for slow clock sys- tems 16-lead SOIC (300 mil) Automatic ECC - internal hardware Error Correction Code Software Features generation with single bit error correction Program Suspend and Resume Erase (1 MBps) Erase Suspend and Resume Hybrid sector size option physical set of thirty two 8-KB Status Register provides status of embedded erase or pro- sectors at top or bottom of address space with all remaining gramming operation sectors of 128 KB CFI Compliant allows host system to identify the flash Uniform sector option always erase 512-KB blocks for soft- device and determine its capabilities ware compatibility with higher density and future devices. User-configurable Configuration Register Cycling Endurance Hardware Features 100,000 Program-Erase Cycles on any sector, minimum Hardware Reset input (RESET ) - resets device to standby Data Retention state 20 Year Data Retention, minimum Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00518 Rev. *E Revised May 02, 2019