Intel Ethernet Controller X540 Datasheet Networking Division PRODUCT FEATURES Host Interface General PCIe base specification 2.1 (2.5GT/s or 5GT/s) Serial Flash interface Bus width x1, x2, x4, x8 Configurable LED operation for software or customizing OEM 64-bit address support for systems using more than 4 GB of LED displays physical memory Device disable capability Package size - 25 mm x 25 mm MAC FUNCTIONS Descriptor ring management hardware for transmit and Networking receive 10 GbE/1 GbE/100 Mb/s copper PHYs integrated on-chip ACPI register set and power down functionality supporting D0 and D3 states Support for jumbo frames of up to 15.5 KB A mechanism for delaying/reducing transmit interrupts Flow control support: send/receive pause frames and receive FIFO thresholds Software-controlled global reset bit (resets everything except the configuration registers) Statistics for management and RMON Four Software-Definable Pins (SDP) per port 802.1q VLAN support Wake up TCP segmentation offload: up to 256 KB IPv6 wake-up filters IPv6 support for IP/TCP and IP/UDP receive checksum offload Configurable flexible filter (through NVM) Fragmented UDP checksum offload for packet reassembly LAN function disable capability Message Signaled Interrupts (MSI) Programmable memory transmit buffers (160 KB/port) Message Signaled Interrupts (MSI-X) Default configuration by NVM for all LEDs for pre-driver Interrupt throttling control to limit maximum interrupt rate functionality and improve CPU usage Flow Director (16 x 8 and 32 x 4) Manageability 128 transmit queues SR-IOV support Receive packet split header Eight VLAN L2 filters Receive header replication 16 Flex L3 port filters Dynamic interrupt moderation Four Flexible TCO filters DCA support Four L3 address filters (IPv4) TCP timer interrupts Advanced pass through-compatible management packet No snoop transmit/receive support Relaxed ordering SMBus interface to an external Manageability Controller (MC) Support for 64 virtual machines per port (64 VMs x 2 queues) NC-SI interface to an external MC Support for Data Center Bridging (DCB) (802.1Qaz, Four L3 address filters (IPv6) 802.1Qbb, 802.1p) Four L2 address filters Order 333168-003 Revision Number: 3.1 February 2020X540 Revisions No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications and roadmaps. The products and services described may contain defects or errors which may cause deviations from published specifications. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548- 4725 or by visiting www.intel.com/design/literature.htm. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries. * Other names and brands may be claimed as the property of others. 2020 Intel Corporation. 2