JL82599EN S R1ZS Intel

Intel 82599 10 GbE Controller Datasheet Ethernet Networking Division (ND) PRODUCT FEATURES General Host Interface Dual port 10 GbE device or Single Port device (82599EN) Serial Flash Interface PCIe Base Specification 2.0 (2.5GT/s) or (5GT/s) 4-wire SPI EEPROM Interface Bus width x1, x2, x4, x8 Configurable LED operation for software or OEM 64-bit address support for systems using more than 4 GB of customization of LED displays physical memory Protected EEPROM space for private configuration Device disable capability MAC FUNCTIONS Package Size - 25 mm x 25 mm Networking Descriptor ring management hardware for transmit and Complies with the 10 Gb/s and 1 Gb/s Ethernet/802.3ap (KX/ receive KX4/KR) specification ACPI register set and power down functionality supporting Complies with the 10 Gb/s Ethernet/802.3ae (XAUI) D0 and D3 states specification A mechanism for delaying/reducing transmit interrupts Complies with the 1000BASE-BX specification Software-controlled global reset bit (resets everything Complies with the IEEE 802.3x 100BASE-TX specification except the configuration registers) Support for jumbo frames of up to 15.5 KB Eight Software-Definable Pins (SDP) per port Auto negotiation Clause 73 for supported mode Four of the SDP pins can be configured as general-purpose CX4 per 802.3ak interrupts Flow control support: send/receive pause frames and receive Wake up FIFO thresholds Ipv6 wake-up filters Statistics for management and RMON Configurable flexible filter (through EEPROM) 802.1q VLAN support LAN function disable capability TCP segmentation offload: up to 256 KB Programmable memory transmit buffers (160 KB/port) IPv6 support for IP/TCP and IP/UDP receive checksum offload Default configuration by EEPROM for all LEDs for pre-driver Fragmented UDP checksum offload for packet reassembly functionality Message Signaled Interrupts (MSI) Support for SR-IOV Message Signaled Interrupts (MSI-X) Interrupt throttling control to limit maximum interrupt rate Manageability and improve CPU usage Receive packet split header Eight VLAN L2 filters Multiple receive queues (Flow Director) 16 x 8 and 32 x 4 16 flex L3 port filters 128 transmit queues Four Flexible TCO filters Receive header replication Four L3 address filters (IPv4) Dynamic interrupt moderation Advanced pass through-compatible management packet DCA support transmit/receive support TCP timer interrupts SMBus interface to an external manageability controller Relaxed ordering NC-SI interface to an external manageability controller Support for 64 virtual machines per port (64 VMs x 2 queues) Four L3 address filters (IPv6) Support for Data Center Bridging (DCB)(802.1Qaz, 802.1Qbb, Four L2 address filters 802.1p) November 2019 Revision 3.4 331520-005 Intel 82599 10 GbE ControllerRevision History Revision History Rev Date Comments 0.5 May 2008 Initial release (Intel Confidential). This release contains advanced information. 0.6 October 2008 Updated to reflect developments, corrections. 0.75 February 2009 Major update (all sections) Reflects latest device developments and corrections. 0.76 March 2009 Updated the following sections: Programming Interface, Manageability, NVM, Initialization, Power Management, and Interconnects. 1.0 March 2009 Major update (all sections) Reflects latest device developments and corrections. 1.5 May 2009 Major update (all sections) Reflects latest device developments and corrections. 1.9 June 2009 Minor update (all sections) Reflects latest device developments and corrections. 2.0 July 2009 Initial release (Intel Public). 2.01 July 2009 Added x8 lane note to Section 1.2.1. 2.1 October 2009 Changed jumbo frame size from KB to bytes (all occurrences). Changed XTAL 25 MODE to RSVDAC6 VCC. Updated section 2.1.4 (changed type from T/s to O). Added F20 and H7 to the table in section 2.1.12. Changed OSC FREQ SEL to RSVDAC6 VCC. Corrected PCIe versions to PCIe V2.0 (2.5GT/s or 5GT/s). Updated the table in section 3.2.7.2.1 (added text to the vendor ID column). Updated the jumbo frame calculations in sections 3.7.7.3.3, 3.7.7.3.4, and 3.7.7.3.5. Added section 4.6.13 Alternate MAC Address Support. Updated section 5.2.2 Auxiliary Power Usage. Added text to section 6.3.6 Alternate Ethernet MAC Address - Word Address 0x37. Updated Table 6.1 (added /1 to row 4). Updated section 6.4.5.8. Added L34TIMIR register name to the Queue Enable bit in section 8.2.3.7.19. Corrected the D10GMP and LMS bit descriptions in section 8.2.3.22.19. Corrected the LP AN page D low bit description in section 8.2.3.22.23. Updated the PRDC bit description is section 8.2.3.23.75. Changed the bit length (31 to 8 to 31 to 0) to the table heading in section 8.2.3.25.12. Updated the Restart AN bit description in section 8.2.3.23.22. Corrected the bit 8 description in section 9.3.7.1.4. Updated section 10.2.2.2.4 (bits RAGEN and TFOENODX read/write value). Added text Jumbo packets above 2 KB . to Filtering exceptions in section 10.3.1. Correct the Buffer Length (byte 1) description in section 10.5.3.8.2. Changed the title of table 11.6, 11.7, and 11.8. Changed Watts to mW in the Power row of table 11.6. Updated the power values in table 11.7 and 11.8. Updated the mechanical package drawing in section 11.5.4. 2 331520-005