IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 JANUARY 2015 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM FEATURES DESCRIPTION The 36Mb IS61DDB21M36A and IS61DDB22M18A are 1Mx36 and 2Mx18 configuration available. synchronous, high-performance CMOS static random access On-chip delay-locked loop (DLL) for wide data valid memory (SRAM) devices. These SRAMs have a common I/O window. bus. The rising edge of K clock initiates the read/write Common I/O read and write ports. operation, and all internal operations are self-timed. Refer to Synchronous pipeline read with self-timed late write the Timing Reference Diagram for Truth Table for a operation. description of the basic operations of these DDR-II (Burst of Double Data Rate (DDR) interface for read and 2) CIO SRAMs. write input ports. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in Fixed 2-bit burst for read and write operations. double data rate. Clock stop support. The following are registered internally on the rising edge of Two input clocks (K and K ) for address and control the K clock: registering at rising edges only. Read/write address Two input clocks (C and C ) for data output control. Read enable Two echo clocks (CQ and CQ ) that are delivered Write enable simultaneously with data. Byte writes for first burst address +1.8V core power supply and 1.5V to 1.8V VDDQ, Data-in for first burst address used with 0.75V to 0.9V VREF. The following are registered on the rising edge of the K HSTL input and output interface. clock: Registered addresses, write and read controls, byte Byte writes for second burst address writes, data in, and data outputs. Data-in for second burst address Full data coherency. Boundary scan using limited set of JTAG 1149.1 Byte writes can change with the corresponding data-in to functions. enable or disable writes on a per-byte basis. An internal write Byte write capability. buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle Fine ball grid array (FBGA) package: later than the write command signal, and the second burst is 13mmx15mm and 15mmx17mm body size timed to the following rising edge of the K clock. 165-ball (11 x 15) array During the burst read operation, the data-outs from the first Programmable impedance output drivers via 5x bursts are updated from output registers of the second rising user-supplied precision resistor. edge of the C clock (starting one and half cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the C clock. The K and K clocks are used to time the data-outs whenever the C and C clocks are tied high. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces. Copyright 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. B 10/02/2014 IS61DDB22M18A IS61DDB21M36A Package ballout and description x36 FBGA Ball Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 1 1 CQ NC/SA SA R/W BW K BW LD SA NC/SA CQ A 2 1 NC DQ27 DQ18 SA BW K BW SA NC NC DQ8 B 3 0 NC NC DQ28 V SA SA SA V NC DQ17 DQ7 C SS 0 SS NC DQ29 DQ19 V V V VSS V NC NC DQ16 D SS SS SS SS NC NC DQ20 V V V VSS V NC DQ15 DQ6 E DDQ SS SS DDQ NC DQ30 DQ21 V V V V V NC NC DQ5 F DDQ DD SS DD DDQ NC DQ31 DQ22 V V V V V NC NC DQ14 G DDQ DD SS DD DDQ D V V V V V V V V V ZQ H off REF DDQ DDQ DD SS DD DDQ DDQ REF NC NC DQ32 V V V V V NC DQ13 DQ4 J DDQ DD SS DD DDQ NC NC DQ23 V V V V V NC DQ12 DQ3 K DDQ DD SS DD DDQ NC DQ33 DQ24 V V V V V NC NC DQ2 L DDQ SS SS SS DDQ NC NC DQ34 V V V V V NC DQ11 DQ1 M SS SS SS SS SS NC DQ35 DQ25 V SA SA SA V NC NC DQ10 N SS SS NC NC DQ26 SA SA C SA SA NC DQ9 DQ0 P TDO TCK SA SA SA C SA SA SA TMS TDI R Notes: 1. The following balls are reserved for higher densities: 10A for 72Mb and 2A for 144Mb. x18 FBGA Ball Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 1 1 CQ NC/SA SA R/W BW K NC/SA LD SA SA CQ A 1 1 NC DQ9 NC SA NC/SA K BW SA NC NC DQ8 0 B NC NC NC V SA SA SA V NC DQ7 NC C SS 0 SS NC NC DQ10 V V V VSS V NC NC NC D SS SS SS SS NC NC DQ11 V V V VSS V NC NC DQ6 DDQ SS SS DDQ E NC DQ12 NC V V V V V NC NC DQ5 F DDQ DD SS DD DDQ NC NC DQ13 V V V V V NC NC NC G DDQ DD SS DD DDQ D V V V V V V V V V ZQ H off REF DDQ DDQ DD SS DD DDQ DDQ REF NC NC NC V V V V V NC DQ4 NC J DDQ DD SS DD DDQ NC NC DQ14 V V V V V NC NC DQ3 DDQ DD SS DD DDQ K NC DQ15 NC V V V V V NC NC DQ2 L DDQ SS SS SS DDQ NC NC NC V V V V V NC DQ1 NC M SS SS SS SS SS NC NC DQ16 V SA SA SA V NC NC NC N SS SS NC NC DQ17 SA SA C SA SA NC NC DQ0 P TDO TCK SA SA SA C SA SA SA TMS TDI R Notes: 1. The following balls are reserved for higher densities: 2A for 72Mb, 7A for 144Mb, 5B for 288Mb, Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. B 10/02/2014