. 36 Mb (1M x 36 & 2M x 18) I DDR-II (Burst of 2) CIO Synchronous SRAMs Two echo clocks (CQ and CQ) that are delivered Features simultaneously with data. 1M x 36 or 2M x 18. +1.8V core power supply and 1.5, 1.8V V , DDQ On-chip delay-locked loop (DLL) for wide data used with 0.75, 0.9V V . REF valid window. HSTL input and output levels. Common data input/output bus. Registered addresses, write and read controls, Synchronous pipeline read with self-timed late byte writes, data in, and data outputs. write operation. Full data coherency. Double data rate (DDR-II) interface for read and Boundary scan using limited set of JTAG 1149.1 write input ports. functions. Fixed 2-bit burst for read and write operations. Byte write capability. Clock stop support. Fine ball grid array (FBGA) package Two input clocks (K and K) for address and con- - 15mm x 17mm body size trol registering at rising edges only. - 1mm pitch Two input clocks (C and C) for data output con- - 165-ball (11 x 15) array trol. Programmable impedance output drivers via 5x user-supplied precision resistor. Description The 36Mb IS61DDB21M36 and IS61DDB22M18 The following are registered on the rising edge of are synchronous, high-performance CMOS static the K clock: random access memory (SRAM) devices. Byte writes These SRAMs have a common I/O bus. The rising Data-in for second burst addresses edge of K clock initiates the read/write operation, and all internal operations are self- Byte writes can change with the corresponding data- timed. in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be regis- Refer to the Timing Reference Diagram for Truth tered one cycle later than the write address. The first Table on page 8 for a description of the basic opera- data-in burst is clocked with the rising edge of the tions of these DDR-II (Burst of 2) CIO SRAMs. next K clock, and the second burst is timed to the following rising edge of the K clock. The input addresses are registered on all rising edges of the K clock. The DQ bus operates at During the burst read operation, at the first burst the double data rate for reads and writes. The following data-outs are updated from output registers off the are registered internally on the rising edge of the K second rising edge of the C clock (1.5 cycles later). clock: At the second burst, the data-outs are updated with Read and write addresses the third rising edge of the corresponding C clock Address load (see page 8). The K and K clocks are used to time Read/write enable the data-outs whenever the C and C clocks are tied Byte writes high. Data-in The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces. Integrated Silicon Solution, Inc. 1-800-379-4774 1 Rev. F 05/08/0936 Mb (1M x 36 & 2M x 18) I DDR-II (Burst of 2) CIO Synchronous SRAMs x36 FBGA Pinout (Top View) 12 34 56 78 9 10 11 ACQ V /SA* SA R/W BW K BW LD SA V /SA* CQ SS 2 1 SS B NC DQ27 DQ18 SA BW KBW SA NC NC DQ8 3 0 CNC NC DQ28 V SA SA SA V NC DQ17 DQ7 SS 0 SS DNCDQ29 DQ19 V V V V V NC NC DQ16 SS SS SS SS SS ENC NC DQ20 V V V V V NC DQ15 DQ6 DDQ SS SS SS DDQ F NC DQ30 DQ21 V V V V V NC NC DQ5 DDQ DD SS DD DDQ G NC DQ31 DQ22 V V V V V NC NC DQ14 DDQ DD SS DD DDQ HDoff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF JNC NC DQ32 V V V V V NC DQ13 DQ4 DDQ DD SS DD DDQ KNC NC DQ23 V V V V V NC DQ12 DQ3 DDQ DD SS DD DDQ L NC DQ33 DQ24 V V V V V NC NC DQ2 DDQ SS SS SS DDQ MNC NC DQ34 V V V V V NC DQ11 DQ1 SS SS SS SS SS NNCDQ35 DQ25 V SA SA SA V NC NC DQ10 SS SS P NC NC DQ26 SA SA C SA SA NC DQ9 DQ0 R TDO TCK SASASA C SA SA SA TMS TDI The following pins are reserved for higher densities: 2A for 144Mb, 10A for 72Mb. BW controls writes to DQ0DQ8 BW controls writes to DQ9DQ17 BW controls writes to DQ18DQ26 BW controls 0 1 2 3 writes to DQ27DQ35. x18 FBGA Pinout (Top View) 12 34 56 78 9 10 11 ACQ V /SA* SA R/W BW K NC/SA LD SA SA CQ SS 1 B NC DQ9 NC SA NC/SA K BW SA NC NC DQ8 0 CNC NC NC V SA SA SA V NC DQ7 NC SS 0 SS DNC NC DQ10 V V V V V NC NC NC SS SS SS SS SS ENC NC DQ11 V V V V V NC NC DQ6 DDQ SS SS SS DDQ FNC DQ12 NC V V V V V NC NC DQ5 DDQ DD SS DD DDQ GNC NC DQ13 V V V V V NC NC NC DDQ DD SS DD DDQ HDoff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF JNC NC NC V V V V V NC DQ4 NC DDQ DD SS DD DDQ KNC NC DQ14 V V V V V NC NC DQ3 DDQ DD SS DD DDQ LNC DQ15 NC V V V V V NC NC DQ2 DDQ SS SS SS DDQ MNC NC NC V V V V V NC DQ1 NC SS SS SS SS SS NNC NC DQ16 V SA SA SA V NC NC NC SS SS P NC NC DQ17 SA SA C SA SA NC NC DQ0 R TDO TCK SASASA C SA SA SA TMS TDI The following pin is reserved for higher densities: 2A for 72Mb, 7A for 144Mb, 5B for 288Mb. BW controls writes to DQ0DQ8 BW controls writes to DQ9DQ17 0 1 2 Integrated Silicon Solution, Inc. 1-800-379-4774 Rev. F 05/08/09