IS61LF102436A IS61VF102436A IS61LF204818A IS61VF204818A 1M x 36, 2M x 18 36Mb SYNCHRONOUS FLOW-THROUGH APRIL 2008 STATIC RAM FEATURES DESCRIPTION The ISSI IS61LF/VF102436A and IS61LF/VF204818A Inter nal self-timed wr ite cycle are high-speed, low-power synchronous static RAMs de- Individual Byte Wr ite Control and Global Wr ite signed to provide burstable, high-performance memory for communication and networking applications. The IS61LF/ Clock controlled, registered address, data and VF102436A is organized as 1,048,476 words by 36 bits. control The IS61LF/VF204818A is organized as 2M-words by 18 Burst sequence control using MODE input bits. Fabricated with ISSI s advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed Three chip enable option for simple depth expan- SRAM core, and high-dr ive capability outputs into a single sion and address pipelining monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single Common data inputs and data outputs clock input. Auto Power-down dur ing deselect Wr ite cycles are inter nally self-timed and are initiated by the Single cycle deselect r ising edge of the clock input. Wr ite cycles can be one to four bytes wide as controlled by the write control inputs. Snooze MODE for reduced-power standby Separate byte enables allow individual bytes to be written. Power Supply Byte wr ite operation is perfor med by using byte wr ite en- able (BWE) input combined with one or more individual LF: Vdd 3.3V + 5%, Vqdd 3.3V/2.5V + 5% byte write signals (BWx). In addition, Global Wr ite (GW) VF: Vdd 2.5V + 5%, Vddq 2.5V + 5% is available for writing all bytes at one time, regardless of the byte write controls. JEDEC 100-Pin TQFP and 165-pin PBGA pack- ages. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) Lead-free available input pins. Subsequent burst addresses can be gener- ated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Inter- leave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter -6.5 -7.5 Units tkq Clock Access Time 6.5 7.5 ns tkc Cycle Time 7.5 8.5 ns Frequency 133 117 MHz Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. 1 Rev. B 04/17/08IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A BLOCK DIAGRAM MODE A0 Q0 CLK CLK A0 BINARY COUNTER A1 Q1 ADV CE A1 1Mx36 ADSC 2Mx18 CLR ADSP MEMORY ARRAY 20/21 18/19 20/21 D Q A ADDRESS REGISTER CE CLK 36, 36, or 18 or 18 GW D Q DQ(a-d) BWE BYTE WRITE BW(a-d) REGISTERS x18: a,b x36: a-d CLK 36, CE 2/4/8 or 18 INPUT CE2 D Q REGISTERS DQa - DQd CE2 ENABLE OE REGISTER CLK CE CLK POWER ZZ DOWN OE 2 Integrated Silicon Solution, Inc. Rev. B 04/17/08