IS61LF25636A IS61VF25636AIS64LF25636A IS61LF51218AIS61VF51218A 256Kx 36, 512Kx18 9MbSYNCHRONOUSFLO W-THROUGH SEPTEMBER2010 STATICRAM FEATURES DESCRIPTION The ISSI IS61LF/VF25636A, IS64LF25636A and IS61LF/ Internal self-timed write cycle VF51218A are high-speed, low-power synchronous Individual Byte Write Control and Global Write static RAMs designed to provide burstable, high-performance memory for communication and networking applications. Clock controlled, registered address, data and The IS61LF/VF25636A and IS64LF25636A are organized control as 262,144 words by 36 bits. The IS61LF/VF51218A is Burst sequence control using MODE input organized as 524,288 words by 18 bits. Fabricated with ISSI s advanced CMOS technology, the device integrates Three chip enable option for simple depth expan- a 2-bit burst counter, high-speed SRAM core, and high- sion and address pipelining drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by Common data inputs and data outputs a positive-edge-triggered single clock input. Auto Power-down during deselect Write cycles are internally self-timed and are initiated by the Single cycle deselect rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Snooze MODE for reduced-power standby Separate byte enables allow individual bytes to be written. JTAG Boundary Scan for PBGA package Byte write operation is performed by using byte write en- able (BWE) input combined with one or more individual Power Supply byte write signals (BWx). In addition, Global Write (GW) LF: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% is available for writing all bytes at one time, regardless of the byte write controls. VF: Vdd 2.5V + 5%, Vddq 2.5V + 5% Bursts can be initiated with either ADSP (Address Status JEDEC 100-Pin TQFP, 119-pin PBGA, and 165- Processor) or ADSC (Address Status Cache Controller) pin PBGA packages input pins. Subsequent burst addresses can be gener- Lead-free available ated internally and controlled by the ADV (burst address advance) input pin. Automotive temperature available The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Inter- leave burst is achieved when this pin is tied HIGH or left floating. FASTACCESS TIME Symbol Parameter -6.5 -7.5 Units tkq Clock Access Time 6.5 7.5 ns tkc Cycle Time 7.5 8.5 ns Frequency 133 117 MHz Copyright 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. H 07/22/2010IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A BLOCK DIAGRAM MODE A0 Q0 CLK CLK A0 BINARY COUNTER A1 Q1 ADV CE A1 256Kx36 ADSC 512Kx18 CLR ADSP MEMORY ARRAY 18/19 16/17 18/19 D Q A ADDRESS REGISTER CE CLK 36, 36, or 18 or 18 D Q GW DQ(a-d) BWE BYTE WRITE BW(a-d) REGISTERS x18: a,b x36: a-d CLK 36, CE 2/4/8 or 18 INPUT CE2 D Q REGISTERS DQa - DQd CE2 ENABLE OE REGISTER CLK CE CLK POWER ZZ DOWN OE 2 Integrated Silicon Solution, Inc. Rev. H 07/22/2010