Long-term Support IS61LF6436A World Class Quality IS61LF6432A 64Kx32, 64Kx36 SYNCHRONOUS FLOW-THROUGH STATIC RAM MAY 2017 DESCRIPTION FEATURES The ISSI IS61LF6432A and IS61LF6436A are high-speed, Internal self-timed write cycle low-power synchronous static RAM designed to provide Individual Byte Write Control and Global Write a burstable, high-performance , memory. IS61LF6432A is organized as 65,536 words by 32 bits. IS61LF6436A is Clock controlled, registered address, data and organized as 65,536 words by 36 bits. They are fabricated control with ISSI s advanced CMOS technolog y. The device inte- Interleaved or linear burst sequence control us - grates a 2-bit burst counter, high-speed SRAM core, and ing MODE input high-drive capability outputs into a single monolithic circuit. Three chip enables for simple depth expansion All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. and address pipelining Common data inputs and data outputs Write cycles are internally self-timed and are initiated by the Power-down control by ZZ input rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. JEDEC 100-Pin TQFP package Power Supply: Separate byte enables allow individual bytes to be writ- +3.3V Vdd ten. BWa controls DQa, BWb controls DQb, BWc controls DQc, BWd controls DQd, conditioned by BWE being LOW. +3.3V or 2.5V Vddq A LOW on GW input would cause all bytes to be written. Control pins mode upon power-up: MODE in interleave burst mode Bursts can be initiated with either ADSP (Address Status ZZ in normal operation mode Processor) or ADSC (Address Status Cache Controller) Industrial Temperature Available: input pins. Subsequent burst addresses can be generated o o internally by the IS61LF6432A /36A and controlled by the (-40 C to +85 C) ADV (burst address advance) input pin. Lead-free available The mode pin is used to select the burst sequence order. Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter 8.5 Unit tkq Clock Access Time 8.5 ns tkc Cycle Time 11 ns Frequency 90 MHz Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex- pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. B1 05/08/2017 IS61LF6436A Long-term Support World Class Quality IS61LF6432A BLOCK DIAGRAM MODE A0 Q0 CLK CLK BINARY COUNTER A1 ADV CE Q1 64Kx32 ADSC 64Kx36 CLR ADSP MEMORY ARRAY A0, A1 17/18 14 16 A D Q ADDRESS REGISTER CE CLK 32, 36 32, 36 D Q GW DQ(a-d) BWE BYTE WRITE BW(a-d) REGISTERS x32/x36: a-d CLK CE 4 32, 36 INPUT CE2 D Q REGISTERS DQa - DQd CE2 ENABLE OE REGISTER CLK CE CLK OE 2 Integrated Silicon Solution, Inc. 1-800-379-4774 Rev. B1 05/08/2017