IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A 64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE NO WAIT STATE BUS SRAM PRELIMINARY INFORMATION SEPTEMBER 2005 FEATURES DESCRIPTION The 2 Meg NLP/NVP produc t family feature high-speed, 100 percent bus utilization low-power synchronous static RAMs designed to provide No wait cycles between Read and Write a burstable, high-performanc e, no wait state, device for Internal self-timed write cycle networking and communications applications. They are organized as 64K words by 32 bits, 64K words by 36 Individual Byte Write Control bits, and 128K words by 18 bits, fabricated with ISSI s Single R/W (Read/Write) control pin advanced CMOS technology. Clock controlled, registered address, Incorporating a no wait state feature, wait cycles are data and control eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, Interleaved or linear burst sequence control us - high-speed SRAM core, and high-drive capability outputs ing MODE input into a single monolithic circuit. Three chip enables for simple depth expansion All synchronous inputs pass through registers are controlled and address pipelining by a positive-ed ge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored Power Down mode when Clock Enable, CKE is HIGH. In this state the internal Common data inputs and data outputs device will hold their previous values. CKE pin to enable clock and suspend operation All Read, Write and Deselect cycles are initiated by the ADV JEDEC 100-pin TQFP package input. When the ADV is HIGH the internal burst counter is incremented . New external addresses can be loaded Power supply: when ADV is LOW. NVP: Vdd 2.5V ( 5%), Vddq 2.5V ( 5%) Write cycles are internally self-timed and are initiated by NLP: Vdd 3.3V ( 5%), Vddq 3.3V/2.5V ( 5%) the rising edge of the clock inputs and when WE is LOW. Industrial temperature available Separate byte enables allow individual bytes to be written. Lead-free available A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol Parameter -250 -200 Units tkq Clock Access Time 2.6 3.1 ns tkc Cycle Time 4 5 ns Frequency 250 200 MHz Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. 00A 08/31/05IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A BLOCK DIAGRAM 64Kx32 A2-A15 or A2-A16 x 32/x 36: A 0:15 or ADDRESS 64Kx36 x 18: A 0:16 REGISTER 128Kx18 MEMORY ARRAY MODE BURST ADDRESS K DATA-IN A0-A1 A 0-A 1 COUNTER REGISTER K DATA-IN WRITE WRITE CLK CONTROL REGISTER ADDRESS ADDRESS LOGIC K CKE REGISTER REGISTER CE CE2 CE2 CONTROL ADV K REGISTER CONTROL OUTPUT WE LOGIC REGISTER BWX (X=a,b,c,d or a,b) BUFFER OE ZZ 32, 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 Rev. 00A 08/31/05