IS61VPD25636a IS61LPD25636a Long-term Support World Class Quality IS61VPD51218a IS61LPD51218a 256K x 36, 512K x 18 JUNE 2017 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STaTIC RaM FEaTURES DESCRIPTION The ISSI IS61LPD/VPD25636A and IS61LPD/VP- Inter nal self-timed wr ite cycle D51218A are high-speed, low-power synchronous static Individual Byte Wr ite Control and Global Wr ite RAMs designed to provide burstable, high-performance memory for communication and networking applications. Clock controlled, registered address, data and The IS61LPD/VPD25636A is organized as 262,144 words control by 36 bits, and the IS61LPD/VPD51218A is organized as Burst sequence control using MODE input 524,288 words by 18 bits. Fabr icated with ISSI s advanced CMOS technology, the device integrates a 2-bit burst Three chip enable option for simple depth ex- counter, high-speed SRAM core, and high-dr ive capability pansion and address pipelining outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive- Common data inputs and data outputs edge-triggered single clock input. Auto Power-down dur ing deselect Wr ite cycles are inter nally self-timed and are initiated by the Double cycle deselect r ising edge of the clock input. Wr ite cycles can be one to four bytes wide as controlled by the write control inputs. Snooze MODE for reduced-power standby Separate byte enables allow individual bytes to be written. JTAG Boundar y Scan for PBGA package The byte wr ite operation is perfor med by using the byte wr ite enable (BWE) input combined with one or more individual Power Supply byte write signals (BWx). In addition, Global Wr ite (GW) LPD: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% is available for writing all bytes at one time, regardless of the byte write controls. VPD: Vdd 2.5V + 5%, Vddq 2.5V + 5% Bursts can be initiated with either ADSP (Address Status JEDEC 100-Pin TQFP, Processor) or ADSC (Address Status Cache Controller) 119-pin PBGA and 165-pin PBGA package input pins. Subsequent burst addresses can be gener- Lead-free available ated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Inter- leave burst is achieved when this pin is tied HIGH or left floating. FaST a CCESS TIME Symbol Parameter 250 200 Units tkq Clock Access Time 2.6 3.1 ns tkc Cycle Time 4 5 ns Frequency 250 200 MHz Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil- ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1-800-379-4774 1 Rev. C1 05/31/2017 Long-term Support IS61VPD25636a IS61LPD25636a World Class Quality IS61VPD51218a IS61LPD51218a BLOCK DIAGRAM MODE A0 Q0 CLK CLK A0 BINARY COUNTER A1 Q1 ADV CE A1 256Kx36 ADSC 512Kx18 CLR ADSP MEMORY ARRAY 18/19 16/17 18/19 A D Q ADDRESS REGISTER CE CLK 36, 36, or 18 or 18 GW D Q DQ(a-d) BWE BYTE WRITE BW(a-d) REGISTERS x18: a,b x36: a-d CLK 36, CE 2/4/8 or 18 INPUT OUTPUT CE2 D Q REGISTERS REGISTERS DQa - DQd CE2 ENABLE OE REGISTER CLK CLK CE CLK D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. 1-800-379-4774 Rev. C1 05/31/2017