IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B 1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, NOVEMBER 2017 SINgLE CYCLE DESELECT STATIC RAM FEATURES DESCRIPTION The 36Mb product family features high-speed, low-power Inter nal self-timed wr ite cycle synchronous static RAMs designed to provide burstable, Individual Byte Wr ite Control and Global Wr ite high-perfor mance memor y for communication and net- wor king applications. The IS61LPS/VPS102436B and Clock controlled, registered address, data and IS64LPS102436B are organized as 1,048,476 words by control 36 bits. The IS61LPS102432B is organized as 1,048,476 Burst sequence control using MODE input words by 32 bits. The IS61LPS/VPS204818B is organized as 2,096,952 words by 18 bits. Fabr icated with ISSI s Three chip enable option for simple depth ex- advanced CMOS technology, the device integrates a pansion and address pipelining 2-bit burst counter, high-speed SRAM core, and high- dr ive capability outputs into a single monolithic circuit. All Common data inputs and data outputs synchronous inputs pass through registers controlled by Auto Power-down dur ing deselect a positive-edge-tr iggered single clock input. Single cycle deselect Wr ite cycles are inter nally self-timed and are initiated by the r ising edge of the clock input. Wr ite cycles can be Snooze MODE for reduced-power standby one to four bytes wide as controlled by the wr ite control JTAG Boundar y Scan for BGA package inputs. Separate byte enables allow individual bytes to be wr itten. Power Supply The byte wr ite operation is perfor med by using the byte LPS: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%) wr ite enable (BWE) input combined with one or more individual byte wr ite signals (BWx). In addition, Global VPS: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%) Wr ite (GW) is available for wr iting all bytes at one time, VVPS: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%) regardless of the byte wr ite controls. JEDEC 100-Pin QFP, 119-ball BGA, and 165- Bursts can be initiated with either ADSP (Address Status ball BGA packages Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be gener- Lead-free available ated inter nally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence or- der, Linear burst is achieved when this pin is tied LOW. Inter leave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter 250 200 166 Units tkq Clock Access Time 2.8 3.1 3.8 ns tkc Cycle Time 4 5 6 ns Frequency 250 200 166 MHz Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. C 11/03/2017IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B BLOCK DIAGRAM MODE A0 A0 CLK Q0 BINARY /CKE COUNTER A1 A1 Q1 /ADV /CE /ADSC /CLR /ADSP 20/21 1Mx36 2Mx18 D Q Memory Array A0-x ADDRESS x18: x=20 18/19 REGISTER x36: x=19 /CE CLK /GW D Q /BWE DQ(a-d) BYTE WRITE /BW(a-x) REGISTERS x18:x=b, INPUT x32,x36:x=d REGISTER CLK /CE D Q CE2 CLK ENABLE /CE2 OUTPUT REGISTERS DQ(a-x) REGISTER x18:x=b, x32,x36:x=d CLK CLK Power ZZ Down D Q ENABLE DELAY REGISTERS CLK /OE 2 Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 Rev. C 11/03/2017