IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC 128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM APRIL 2017 FEATURES DESCRIPTION The 4Mb product family features high-speed, low-power Internal self-timed write cycle synchronous static RAMs designed to provide burstable, Individual Byte Write Control and Global Write high-performance memory for communication and networking applications. The IS61(64)LPS/VPS12836EC are Clock controlled, registered address, data and organized as 131,072 words by 36bits. The control IS61(64)LPS/VPS12832EC are organized as 131,072 words by 32bits. The IS61(64)LPS/VPS25618EC are organized as Burst sequence control using MODE input 262,144 words by 18 bits. Fabricated with ISSI s advanced CMOS technology, the device integrates a 2-bit burst Three chip enable option for simple depth counter, high-speed SRAM core, and high-drive capability expansion and address pipelining outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive- Common data inputs and data outputs edge-triggered single clock input. Auto Power-down during deselect Write cycles are internally self-timed and are initiated by Single cycle deselect the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Snooze MODE for reduced-power standby JEDEC 100-pin QFP, 165-ball BGA and 119- Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte ball BGA packages write enable (/BWE) input combined with one or more individual byte write signals (/BWx). In addition, Global Power supply: Write (/GW) is available for writing all bytes at one time, LPS: VDD 3.3V ( 5%), VDDQ 3.3V/2.5V ( 5%) regardless of the byte write controls. VPS: VDD 2.5V ( 5%), VDDQ 2.5V ( 5%) Bursts can be initiated with either /ADSP (Address Status Processor) or /ADSC (Address Status Cache Controller) JTAG Boundary Scan for BGA packages input pins. Subsequent burst addresses can be generated Industrial and Automotive temperature support internally and controlled by the /ADV (burst address advance) input pin. Lead-free available Error Detection and Error Correction The mode pin is used to select the burst sequence order. Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter -250 -200 Units tKQ Clock Access Time 2.6 3.1 ns tKC Cycle time 4 5 ns fMAX Frequency 250 200 MHz Copyright 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. D2 04/14/2017 IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC BLOCK DIAGRAM Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. D2 04/14/2017