IS61VPS25672A IS61LPS25672A IS61VPS51236A IS61LPS51236A IS61VPS102418A IS61LPS102418A 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, MAY 2010 SINGLE CYCLE DESELECT STATIC RAM DESCRIPTION FEATURES The ISSI IS61LPS/VPS51236A, IS61LPS/VPS102418A, Internal self-timed write cycle and IS61LPS/VPS25672A are high-speed, low-power syn- Individual Byte Write Control and Global Write chronous static RAMs designed to provide burstable, high- performance memory for communication and networking Clock controlled, registered address, data and applications. The IS61LPS/VPS51236A is organized as control 524,288 words by 36 bits, the IS61LPS/VPS102418A is Burst sequence control using MODE input organized as 1,048,576 words by 18 bits, and the IS61LPS/ VPS25672A is organized as 262,144 words by 72 bits. Three chip enable option for simple depth Fabricated with ISSI s advanced CMOS technology, the expansion and address pipelining device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single mono- Common data inputs and data outputs lithic circuit. All synchronous inputs pass through regis- Auto Power-down during deselect ters controlled by a positive-edge-triggered single clock input. Single cycle deselect Write cycles are internally self-timed and are initiated by Snooze MODE for reduced-power standby the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. JTAG Boundary Scan for PBGA package Separate byte enables allow individual bytes to be written. Power Supply The byte write operation is performed by using the byte LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5% Write (GW) is available for writing all bytes at one time, JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball regardless of the byte write controls. PBGA, and 209-ball (x72) packages Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) Lead-free available input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter 250 200 Units tKQ Clock Access Time 2.6 3.1 ns tKC Cycle Time 4 5 ns Frequency 250 200 MHz Copyright 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. 1-800-379-4774 1 Rev. N 02/12/2010IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A BLOCK DIAGRAM MODE A0 Q0 A0 CLK CLK BINARY COUNTER A1 Q1 ADV CE A1 256Kx72 ADSC 512Kx36 CLR ADSP 1024Kx18 MEMORY ARRAY 19/20 17/18 19/20 A D Q ADDRESS REGISTER CE CLK 36, 36, or 18 or 18 or 72 or 72 GW D Q DQ(a-h) BWE BYTE WRITE BW(a-h) REGISTERS x18: a,b x36: a-d CLK x72: a-h 36, CE 2/4/8 or 18 INPUT OUTPUT or 72 CE2 D Q REGISTERS REGISTERS DQa - DQd CE2 ENABLE OE REGISTER CLK CLK CE CLK D Q ENABLE DELAY POWER REGISTER ZZ DOWN CLK OE 2 Integrated Silicon Solution, Inc. 1-800-379-4774 Rev. N 02/12/2010