IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, JUNE 2015 SINg LE CYCLE DESELECT STATIC RAM FEATURES DESCRIPTION The ISSI IS61LPS/VPS25636A, IS61LPS25632A, Inter nal self-timed wr ite cycle IS64LPS25636A and IS61LPS/VPS51218A are high- Individual Byte Wr ite Control and Global Wr ite speed, low-power synchronous static RAMs designed to provide burstable, high-perfor mance memory for com- Clock controlled, registered address, data and munication and networ king applications. The IS61LPS/ control VPS25636A and IS64LPS25636A are organized as Burst sequence control using MODE input 262,144 words by 36 bits. The IS61LPS25632A is organized as 262,144 words by 32 bits. The IS61LPS/ Three chip enable option for simple depth ex- VPS51218A is organized as 524,288 words by 18 bits. pansion and address pipelining Fabr icated with ISSI s advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed Common data inputs and data outputs SRAM core, and high-dr ive capability outputs into a single Auto Power-down dur ing deselect monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-tr iggered single Single cycle deselect clock input. Snooze MODE for reduced-power standby Wr ite cycles are inter nally self-timed and are initiated by JTAG Boundar y Scan for BGA package the r ising edge of the clock input. Wr ite cycles can be one to four bytes wide as controlled by the write control Power Supply inputs. LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% Separate byte enables allow individual bytes to be written. The byte wr ite operation is perfor med by using the byte VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% write enable (BWE) input combined with one or more JEDEC 100-Pin QFP, 119-ball BGA, and 165- individual byte write signals (BWx). In addition, Global ball BGA packages Wr ite (GW) is available for writing all bytes at one time, regardless of the byte write controls. Lead-free available Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be gener- ated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence or- der, Linear burst is achieved when this pin is tied LOW. Inter leave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter 250 200 166 Units tkq Clock Access Time 2.6 3.1 3.5 ns tkc Cycle Time 4 5 6 ns Frequency 250 200 166 MHz Copyright 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. 1 Rev. N 05/25/2015IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A BLOCK DIAGRAM MODE A0 Q0 CLK CLK A0 BINARY COUNTER A1 Q1 ADV CE A1 256Kx32 ADSC 256Kx36 CLR ADSP 512Kx18 MEMORY ARRAY 18/19 16/17 18/19 D Q A ADDRESS REGISTER CE CLK 32, 36, 32, 36, or 18 or 18 D Q GW DQ(a-d) BWE BYTE WRITE BW(a-d) REGISTERS x18: a,b x32/x36: a-d CLK 32, 36, CE 2/4/8 or 18 INPUT OUTPUT CE2 D Q DQa - DQd REGISTERS REGISTERS CE2 ENABLE OE REGISTER CLK CLK CE CLK D Q ENABLE DELAY POWER REGISTER ZZ DOWN CLK OE 2 Integrated Silicon Solution, Inc. Rev. N 05/25/2015